issue of the stimulation of charge-pump phase-locked loops for built-in self-test applications. It is shown that three nodes of the PLL qualify for test signal injection. The hardware and methodology for each are discussed. In particular, a comprehensive explanation of the use of delta-sigma modulation in the time domain is provided. Furthermore, implementation issues of analog tests with signa...

A general-purpose phase-locked loop (PLL) with programmable bit rates is presented demonstrating that large frequency tuning range, large power supply range, and low jitter can be achieved simultaneously. The clock recovery architecture uses phase selection for automatic initial frequency capture. The large period jitter of conventional phase selection is eliminated through feedback phase selec...

This paper proposes an improved sensorless control to estimate the rotor position of an interior permanent magnet synchronous motor. A phase-locked loop (PLL) is used to obtain the phase angle of the grid. The rotor position can be estimated using a PLL based on extended electromotive force (EEMF) because the EEMF contains information about the rotor position. The proposed method can reduce the...

The moving average filter-based phase-locked loop (MAF-PLL) can obtain grid synchronization signals accurately under adverse conditions with a large amount of harmonics due to the high filtering capability MAF. However, MAF-PLL cannot achieve fast dynamic response in case frequency drift, phase angle steps, and unbalanced voltage sag. MAF is essentially an FIR filter, its performance hard be ad...

The Phase-Locked Loop is used to track an incoming signal and provide accurate carrier phase measurements on GPS receivers. However, the PLL performance is affected by the thermal noise and dynamic stress. In order to resolve the conflict between reducing PLL noise and overcoming the dynamic stress, some compromises must be taken in PLL design. This paper proposes a wavelet packet de-noising te...

High-voltage flexible power systems, with their intrinsic characteristics, play an increasingly important role in electronic systems. Synchronization between the inverter and grid needs to be achieved by a phase-locked loop (PLL), performance of which determines quality transmission. This paper proposes PLL adapted extremely harsh conditions. Firstly, traditional synchronous reference frame dua...

This paper revisits the design of current controller for grid-connected voltage-source converters (VSCs), considering dynamic impacts phase-locked loop (PLL), weak grids, and voltage feedforward (VFF) control. First, a single-input single-output transfer-function-based model is proposed to characterize interactions control loops. It analytically found that proportional gain essentially aggravat...

This paper describes the design of a bipolar junction transistor phase-locked loop (PLL) for fractional-N frequency-synthesis applications. Implemented in a 0.8m BiCMOS technology, the PLL can operate up to 1.8 GHz while consuming 225 mW of power from a single 2-V supply. The entire LC-tuned negative-resistance variable-frequency oscillator is integrated on the same chip. A differential low-vol...

The CD4046BC micropower phase-locked loop (PLL) consists of a low power, linear, voltage-controlled oscillator (VCO), a source follower, a zener diode, and two phase comparators. The two phase comparators have a common signal input and a common comparator input. The signal input can be directly coupled for a large voltage signal, or capacitively coupled to the self-biasing amplifier at the sign...

Abstract This study focuses on stability of weak grid connected voltage source converter (WG‐VSC) in Low‐frequency mode (LFM) (around 1–10 Hz), which is dominated by interactions among phase‐locked loop (PLL), outer control and condition. In order to clearly reveal LFM mechanism WG‐VSC, a simple but effective PLL‐equivalent model has been proposed. First, generic small signal consisted PLL ‘out...