The realization of a digital phase-locked loop (DPLL) requires to choose a suitable phase detector and to design an appropriate loop filter; these tasks are commonly nontrivial in most applications. In this paper, the phase detector is examined, and a simple model is given to describe the characteristics of the timing function. The DPLL system is then formulated as a state estimation problem; t...

In this work, a Markov random field based phase locked loop is proposed for phase unwrapping. The neighboring pixels are used to update the phase estimate of the centering pixel. The performance of the proposed method is evaluated for both synthetic and real interferometric phase. For terrains with relatively low slopes, the phase unwrapping is done successfully. However, in case of high fringe...

This paper demonstrates the use of a spreadsheet in exploring non-linear difference equations that describe digital control systems used in radio engineering, communication and computer architecture. These systems, being the focus of intensive studies of mathematicians and engineers over the last 40 years, may exhibit extremely complicated behavior interpreted in contemporary terms as transitio...

The control system of a doubly-fed adjustable-speed pumped-storage hydropower plant needs phase-locked loops (PLLs) to obtain the phase angle of grid voltage. The main drawback of a comb-filter-based phase-locked loop (CF-PLL) is the slow dynamic response. This paper presents a modified comb-filter-based phase-locked loop (MCF-PLL) by improving the pole-zero pattern of the comb filter, and give...

Phase locked loop based feedback techniques are used in a variety of system level timing, control and communication applications. Re-configurable hardware and associated simulation models have been developed with an emphasis towards teaching the fundamentals of Phase locked loop systems. The material is hardware focussed and reinforces, control system theory, characterisation, design, and model...

This paper describes the design of an All-Digital Phase Locked Loop (AD-PLL) for wireless applications in the WiMAX 3.3– 3.8 GHz bandwidth. The time/digital converter (TDC) sets the in-band noise and it may be responsible for the presence of spurious tones at the PLL output. The TDC is implemented as a delay-locked loop (DLL) to be insensitive to process spreads and it uses a lead-lag phase det...

This paper presents a new circuit for clock generation. A new phase frequency detector is designed in 130nm CMOS process technology. The phase locked loop is designed to meet the 10BaseKR wire line communication standards. All the circuits are designed in current mode logic for high speed operation. The designed circuit dissipates mW. The voltage controlled oscillator has phase noise of -182. 2...

This paper deals with Enhanced Phase Locked Loop Control scheme for Distributed Static Compensator (DSTATCOM) in the distribution system. The proposed control scheme based DSTATCOM eliminates current harmonics, maintains unity power factor at source, zero voltage regulation and load balancing. The Enhanced Phase Locked Loop (EPLL) Control scheme is based on Digital Signal Processing (DSP) which...

Phase locked loops (PLL) and delay locked loops (DLL) play an important role in establishing coherent references (phase of carrier and symbol timing) in digital communication systems. Fully digital receiver including digital carrier synchronizer and symbol timing synchronizer fulfils the conditions for universal multi-mode communication receiver with option of symbol rate setting over several d...