Most modern processors have hardware support for single precision and double precision floating point multiplication. For many scientific computations like climate modeling, computational physics and computational geometry this support is inadequate. They impose the use of quadruple precision arithmetic because it provides twice the precision of double precision format. The proposed design perf...

A new GF(2) redundant representation is presented. Squaring in the representation is almost cost-free. Based on the representation, two multipliers are proposed. The XOR gate complexity of the first multiplier is lower than a recently proposed normal basis multiplier when CN (the complexity of the basis) is larger than 3n-1. Index Terms Finite field, normal basis, redundant set, Massey-Omura mu...

In this paper, a new bit-parallel Montgomery multiplier for GF (2) is presented, where the field is generated with an irreducible trinomial. We first present a slightly generalized version of a newly proposed divide and conquer approach. Then, by combining this approach and a carefully chosen Montgomery factor, the Montgomery multiplication can be transformed into a composition of small polynom...

A symmetric key cryptosysteni, called PGM, based on log~ r i t h r n i ~ signatures for finite pcrmutation groups was invented by S. Magliveras in the late 1970's. PGM is intended to be used in cryptosystems with high data rates. This requires exploitation of the potential parallelism in composition of permutations. As a first step towards a full VLSI implementation, a parallel multiplier has b...

This paper is published in: H. Fan, Researches in GF(2) Multiplication Algorithms, PhD dissertation, Tsinghua University, 2004. (in Chinese) Abstract A new GF(2) redundant representation is presented. Squaring in the representation is almost cost-free. Based on the representation, two multipliers are proposed. The XOR gate complexity of the first multiplier is lower than a recently proposed nor...

Multiplier and divider circuits are usually required in the fields of analog signal processing and parallel-computing neural or fuzzy systems. In particular, this paper focuses on the hardware implementation of fuzzy controllers, where the divider circuit is usually the bottleneck. Multiplier/ divider circuits can be implemented with a combination of A/D-D/A converters. An efficient design base...

The multiplier and multiplier-and-accumulator (MAC) are the essential elements of the digital signal processing. Multiplication involves two basic operations: the generation of partial products and their accumulation. Partial products can be reduced by using the Radix_4 modified Booth algorithm. The design of a binary signed-digit partial product generator, which expresses each normal binary op...