We describe a scalable decoder for parsing-based machine translation. e decoder is written in Java and implements all the essential algorithms described in (Chiang, 2007) and (Li and Khudanpur, 2008b): chart-parsing, n-gram language model integration, beamand cube-pruning, and k-best extraction. Additionally, parallel and distributed computing techniques are exploited to make it scalable. We d...

Applying a joint code and decoder design methodology, we develop a high-speed (3, k)-regular LDPC code partly parallel decoder architecture, based on which a 9216-bit, rate1/2 (3, 6)-regular LDPC code decoder is implemented on Xilinx FPGA device. When performing maximum 18 iterations for each code block decoding, this partly parallel decoder supports a maximum symbol throughput of 54 Mbps and a...

Hypothetical Reference Decoder is a hypothetical decoder model that specifies constraints on the variability of conforming network abstraction layer unit streams or conforming byte streams that an encoding process may produce. High Efficiency Video Coding (HEVC) builds upon and improves the design of the generalized hypothetical reference decoder of H.264/ AVC. This paper describes some of the ...

A 1024-b, rate-1/2, soft decision low-density paritycheck (LDPC) code decoder has been implemented that matches the coding gain of equivalent turbo codes. The decoder features a parallel architecture that supports a maximum throughput of 1 Gb/s while performing 64 decoder iterations. The parallel architecture enables rapid convergence in the decoding algorithm to be translated into low decoder ...

—In this paper, MIMO (Multiple-Input-Multiple Output) system based on turbo equalization techniques which LDPC (Low Density Parity Check) codes were outer code and STTC (Space Time Trellis Code) were employed as an inner code are studied. LDPC decoder and STTC decoder are connected through the interleaving and de-interleaving that updates each other's information repeatedly. On the receiver si...

In this paper, a new MBE (modified Booth encoding) recoder, and a new MBE decoder are proposed in CMOS transistor level to improve the performance of traditional multipliers. The proposed pipelined Booth multiplier can reduce the delay time of the critical path by levelizing the complex gate in the MBE decoder. As a result, MBE decoder is no more the speed bottleneck of a pipelined booth multip...