This paper evaluates network caching as a means to improve the performance of cluster-based multiprocessors. A network cache, shared by all processors on each cluster, o ers the potential bene ts of increased intra-cluster sharing, reduced network tra c, and useful prefetching. Using simulation, we evaluate the feasibility, structure, and performance of a network cache implementation. Five well...

Abstract Micro Ring Resonator (MRR) is a successful micro-device with the help of which different types optical logic gates, processors, arithmetic units, etc. can be designed and integrated easily into modern high-speed communication network. In this article, at first, author has explained switching mechanism MRR then an optically controlled Feynman gate (i.e. reversible controlled-Not gate) u...

A snap-stabilizing protocol, starting from any arbitrary initial configuration, always behaves according to its specification. In [4], we presented the first snap-stabilizing depth-first search (DFS) wave protocol for arbitrary rooted networks working under an unfair daemon. However, this protocol needs O(N ) states per processors (where N is the number of processors) and needs ids on processor...

Banked register file has been proposed to reduce die area, power consumption, and access time. Some embedded processors, e.g. Intel’s IXP network processors, adopt this organization. However, they expose some access constraints in ISA, which complicates the design of register allocation. In this paper, we present a register allocation framework for banked register files with access constraints ...

While the primary function of the network in a parallel computer is to communicate data between processors, it is often useful if the network can also perform rudimentary calculations. That is, some simple processing ability in the network itsetf, particularly for performing parallel prefix computations, can reduce both the volume of data being communicated and the computational load on the pro...

A portion of the Cray Red Storm system at Sandia National Laboratories recently completed an upgrade of the processor and network hardware. Single-core 2.0 GHz AMD Opteron processors were replaced with dual-core 2.4 GHz AMD Opterons, while the network interface hardware was upgraded from a sustained rate of 1.1 GB/s to 2.0 GB/s (without changing the router link rates). These changes more than d...

Current multi-core network protocol stack designs use lock-based and scheduler-based approaches to leverage multiple processors. Unfortunately, these approaches limit protocol stack scalability on multicore systems both for high-bandwidth connections and large numbers of concurrent connections. In this paper, we propose a new approach to parallelizing network protocol stacks based on state repl...

Leader Election is a fundamental problem in centralized control of distributed systems. The election process starts when one or more processors discover that the leader has failed, and it terminates when the remaining processors know who the new leader is. This study presents a distributed solution to this problem in Hypercube networks considering the link failure. A distributed leader election...

Mass data processing and complex problem solving have higher and higher demands for performance of multiprocessor systems. Many multiprocessor systems have interconnection networks (networks for short) as underlying topologies and a network is usually represented by a graph where nodes represent processors and links represent communication links between processors. The network determines the pe...

This paper develops two new algorithms for solving a nite constraint satisfaction problem (FCSP) in parallel. In particular, we give a parallel algorithm for the EREW PRAM model and a distributed algorithm for networks of interconnected processors. Both of these algorithms are derived from arc consistency algorithms which are preprocessing algorithms in general, but can be used to solve an FCSP...