In this work, we report transistors made of van der Waals materials on a mesoporous paper with a smooth nanoscale surface. The aqueous transistor has a novel planar structure with source, drain, and gate electrodes on the same surface of the paper, while the mesoporous paper is used as an electrolyte reservoir. These transistors are enabled by an all-cellulose paper with nanofibrillated cellulo...

We have successfully aligned single-walled carbon nanotubes (SWNTs) in patterns with nanoscale width, micron-scale length and controllable pitch on SiO2/Si substrates using a poly(dimethysiloxane) (PDMS) microchannel mold. The microchanneled mold was patterned with a funnel-shaped channel to minimize nanotube jamming during capillary-driven inflow. Two (i.e. preand post-capillary) gas blows wer...

[email protected] [email protected] Abstract— This Paper Deals With the Design and Analysis of 3T1D DRAM Cell to develop Process Variation Architectures using Cadence Tool. With continued technology scaling, process variations will be especially Detrimental to Threetransistor One Diode Dynamic memory structures (3T1D DRAM). A Memory architecture using three-transistor, onediode DRAM...

The impact of dopant atoms in transistor functionality has significantly changed over the past few decades. In downscaled transistors, discrete dopants with uncontrolled positions and number induce fluctuations in device operation. On the other hand, by gaining access to tunneling through individual dopants, a new type of devices is developed: dopant-atom-based transistors. So far, most studies...

Power dissipation due to leakage current in the digital circuits is a biggest factor which is considered specially while designing nanoscale circuits. This paper is exploring the ideas of reducing leakage current in static CMOS circuits by stacking the transistors in increasing numbers. Clearly it means that the stacking of OFF transistors in large numbers result a significant reduction in powe...

Amount of power consumption is one of the important measures of performance of an integrated circuit. CMOS is the latest technology which is in use till date. This paper gives an overview of the power dissipation occurring in CMOS circuit. The paper then describes the advantages and limitations of power optimization techniques of CMOS. As we go deeper into the nanometer scale, MOS transistors f...

We have derived a general formula describing current noise in multimode ballistic channels connecting source and drain electrodes with Fermi electron gas. In particular ~at eV@kBT), the expression describes the nonequilibrium ‘‘shot’’ noise, which may be suppressed by both Fermi correlations and space charge screening. The general formula has been applied to an approximate model of a two-dimens...

2017[9] THE HITACHI SCIENTIFIC INSTRUMENT NEWS ー 2017 Vol.8 Fine-grain control of the structure of materials is widely regarded as a crucial technology undergirding innovation in materials science. Today, thanks to nanotechnology initiatives launched at the beginning of the 21st century, materials and device elements with a fi ne grain structure can be produced and distributed as nano-products....

The field of nanoelectronics and, in particular, the vision of extending complementary metalYoxideY semiconductor (CMOS) and the possibility of discovering new, highly scalable, concepts for information processing and memory functions is becoming an exciting reality. Interdisciplinary research of nanoscale structures embodied in a myriad of new materials at the atomic-scale quantum domain promi...

In suitably designed nanoscale systems the ultrafast migration of uv/visible electromagnetic energy, despite its nearfield rather than propagating character, can be made highly directional. At the photon level such energy migration generally takes a multi-step form, with each step signifying the transfer of an electromagnetic quantum between chromophores playing the transient roles of source/do...