Directory hints help a node in a NOW-based shared memory multiprocessor to keep track where valid copies of a memory block may reside. With this information the node can fetch the block directly from those nodes on a read miss. In this way the number of network transactions to serve the miss may be reduced and the expensive directory lookup operation may be removed from the critical path. In th...

Nowadays, the use of multiprocessor systems is not just limited to typical scientific applications, but these systems are increasingly being used for executing commercial applications, such as databases and web servers. Therefore, it becomes essential to study the behavior of multiprocessor architectures under commercial workloads. To accomplish this, we need simulators able to model not only t...

This paper examines the performance of distributed-shared-memory systems based on the Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) using queueing network models and develops theoretical results which predict processor utilization, message latency and other useful measures. It also presents simulation results which compare the performance of the SOME-Bus, the mesh and the torus us...

Recent advances in the development of reconfigurable optical interconnect technologies allow for the fabrication of low cost and run-time adaptable interconnects in large distributed shared-memory (DSM) multiprocessor machines. This can allow the use of adaptable interconnection networks that alleviate the huge bottleneck present due to the gap between the processing speed and the memory access...

A neural network based technique is introduced which hides the control latency of reconfigurable interconnection networks (INs) in shared memory multiprocessors. Such INs require complex control mechanisms to reconfigure the IN on demand, in order to satisfy processor-memory accesses. Hiding the control latency seen by each access improves multiprocessor performance significantly. The new techn...

The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network that directly links arbitrary pairs of processor nodes without contention, and can efficiently interconnect over one hundred nodes. Each node has a dedicated output channel and an array of receivers, with one receiver dedicated to every other node’s output channel. The SOME-B...

The performance of modern multiprocessor systems is increasingly limited by interconnection delays or long latencies of memory subsystems. Instruction–level multithreading is a technique to tolerate such long latencies by switching from one instruction thread to another and continuing instruction execution concurrently with the long–latency operations. Using timed Petri net models, the paper an...

As transistor size shrinks and chip complexity increases it is possible to place more transistor onto a singe chip, and thus it is possible to integrate more then one processor on a single chip. Clock frequency is also increased, and because of wire delay it is not possible to reach all parts of a chip in a single clock cycle, and interconnection network is becoming a bottleneck in such systems...

Nonuniform traffic patterns can severely degrade the performance of wormhole-routing multistage interconnection networks in multiprocessor systems. A wormhole-routing switch box architecture is proposed that is able to control the degrading effects of saturation trees on the uniform background traffic under nonuniform traffic patterns that are known a priori. An alternating priority mechanism i...

The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network which directly links arbitrary pairs of processor nodes without contention, and can efficiently interconnect over one hundred nodes. Each node has a dedicated output channel and an array of receivers, with one receiver dedicated to every other node’s output channel. The SOME-...