Distributed Arithmetic (DA) has been successfully applied to the design of area efficient multipliers on FPGAs for DSP applications. Whilst DA is efficient in applications where coefficients are fixed, there is little option for applications with a limited range of coefficient values. This paper describes a technique for developing areaefficient multipliers for a range of DSP applications that ...

Until recently, verifying multipliers with formal methods was not feasible, even for small input word sizes. About two years ago, a new data structure, called Multiplicative Binary Moment Diagram (*BMD), was introduced for representing arithmetic functions over Boolean variables. Based on this new data structure, methods were proposed by which veriication of multipliers with input word sizes of...

We describe how a simple way to split input operands allows for fast VLSI implementations of subquadratic GF (2)[x] Karatsuba-Ofman multipliers. The theoretical XOR gate delay of the resulting multipliers is reduced significantly. For example, it is reduced by about 33% and 25% for n = 2 and n = 3 (t > 1), respectively. To the best of our knowledge, this parameter has never been improved since ...

| The Inverse Discrete Cosine Transform (idct) is used in almost all video-decoders, like mpeg and hdtv. In de process of video decoding, the idct is a computationally heavy part. One of the performance characteristics is the power consumption , which is related to the dynamic behavior of the hardware. In this paper the signal transitions that occur in the multipliers are analyzed with vhdl, wh...

Multiplication is one of the basic functions used in digital signal processing (DSP). It requires more hardware resources and processing time than addition and subtraction. In fact, 8.72% of all instructions in a typical processing unit is multiplier. The multiplier is a fairly large block of a computing system. The amount of circuitry involved is directly proportional to square of its resoluti...