This paper presents different approaches for real-time fault tolerance using redundancy methods for multi-core systems. Using hardware virtualization, a distributed system on a chip is created, where the cores are isolated from one another except through explicit communication channels. Using this system architecture, redundant tasks that would typically be run on separate processors can be con...

Recent developments have brought to the forefront some pressing and difficult problems concerning the usability of computer systems: lack of a satisfactory general purpose programming model for parallel computation; how to achieve efficient utilization of processing and memory resources; and system resilience in the presence of malicious attacks and the expectation that future hardware will be ...

-Multicore architecture otherwise called as CMP has many processors packed together on a single chip utilizes hyper threading technology. The main reason for adding large amount of processor core brings massive advancements in parallel computing paradigm. The enormous performance enhancement in multicore platform injects lot of challenges to the task allocation and load balancing on the process...

The multi-comparand associative search paradigm is shown to be efficient in processing complex search problems from many application areas including computational geometry, graph theory, and list/matrix computations. In this paper the first FPGA implementation of a small multi-comparand multi-search associative processor is reported. The architecture of the processor and its functions are descr...

Conform [1], [2] numim multi-processors sistemele cu mai mult de un processor, în timp ce termenul de many-processors este folosit pentru sistemele cu un număr foarte mare de procesoare. Fundamentarea teoretică pentru cele două tipuri de maşini este diferită şi semnificativă pentru înţelegerea evoluţiei ştiinţei calculului în era paralelismului emergent. În timp ce multi-processor-ul este o con...

We propose a novel Viterbi processor for the large vocabulary real-time continuous speech recognition. This processor is built with multi Viterbi cores. Since each core can independently compute, these cores reduce the cycle times very efficiently. To verify the effect of utilizing multi cores, we implement a dual-core Viterbi processor in an FPGA and achieve 49% cycle-time reduction, compared ...