The most research on the power consumption of circuits has been concentrated on the switching power and the power dissipated by the leakage current has been relatively minor area. In today‟s IC design, one of the key challenges is the increase in power dissipation of the circuit which in turn shortens the service time of battery-powered electronics, reduces the longterm reliability of circuits ...

Optical transistor is a device used to amplify and switch optical signals. Many researchers focus on replacing current computer components with optical equivalents, resulting in an optical digital computer system processing binary data. Electronic transistor is the fundamental building block of modern electronic devices. To replace electronic components with optical ones, an equivalent optical ...

The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has been designed using the proposed three-transistor XOR gate and its performance has been inve...

We propose to use the Hall response of topological defects, such as merons and antimerons, spin currents in two-dimensional magnetic insulator with in-plane anisotropy for identification Berezinskii-Kosterlitz-Thouless (BKT) transition a transistorlike geometry. Our numerical results relying on combination Monte Carlo dynamics simulations show from superfluidity conventional transport, accompan...

Quantum-dot cellular automata (QCA), a computation paradigm based on the Coulomb interactions between neighboring cells. The key idea is to represent binary information, not by the state of a current switch (transistor), but rather by the configuration of charge in a bistable cell. In its molecular realization, the QCA cell can be a single molecule. QCA is ideally suited for molecular implement...

This chapter shows a minimum-width transistor placement method which is applicable to CMOS cells in presence of non-dual P and N type transistors, whereas the cell layout synthesis methods explained in the previous chapters are only for dual cells. This chapter only targets the minimum-width transistor placement, and does not take the intra-cell routings into consideration. The proposed method ...