This work explores the data reuse properties of fullsearch block-matching (FSBM) for motion estimation (ME) and associated architecture designs, as well as memory bandwidth requirements. Memory bandwidth in high-quality video is a major bottleneck to designing an implementable architecture because of large frame size and search range. First, memory bandwidth in ME is analyzed and the problem is...

We present design details and some initial performance results of a novel scalable shared memory multiprocessor architecture that incorporates the major strengths of several contemporary multiprocessor architectures while avoiding their most serious weaknesses. Speciically, our architecture design incorporates the automatic data migration and replication features of cache-only memory architectu...

The traditional wisdom for building disk-based relational database management systems (DBMS) is to organize data in heavily-encoded blocks stored on disk, with a main memory block cache. In order to improve performance given high disk latency, these systems use a multi-threaded architecture with dynamic record-level locking that allows multiple transactions to access the database at the same ti...

One of the primary concerns of performing efficient data-intensive computing at scale is the inherent ability to exploit memory bandwidth on a local and global scale. The traditional computer architecture inherently decouples the processing interconnect from the memory interconnect, thus preventing efficient, parallel utilization of both at scale. Further, the orthogonal nature of these board-l...

Embedded systems present a tremendous opportunity to customize the designs by exploiting the application behavior. Shrinking time-to-market, coupled with short product lifetimes create a critical need for rapidly explore and evaluate candidate System-on-Chip(SOC) architectures. Recent work on language driven Design Space Exploration (DSE) uses Architecture Description Language (ADL) to capture ...

The Data-Intensive Architecture (DIVA) system incorporates Processing-In-Memory (PIM) chips as smart-memory coprocessors to a microprocessor. This architecture exploits inherent memory bandwidth both on chip and across the system. Thus, performances of pointer-based and sparse-matrix computations as well as multimedia applications are significantly enhanced. A key feature of the DIVA architectu...

This paper describes a virtually pipelined memory architecture built on a dual-port phase change memory (PCM) substrate for high performance networking applications. The proposed dual-port PCM cell significantly reduces the probability of bank conflicts due to blocking writes, ensuring that the proposed memory architecture can provide the large bandwidth and bank parallelism necessary for such ...

The MULTIPLUSproject aims at the development of a modular parallel architecture suitable for the study of several aspects of parallelism in both true shared memory and virtual shared memory environments. The MULTIPLUS architecture is able to support up to 1024 Processing Elements based on SPARC microprocessors. The MULPLIX Unix-like operating system offers a suitable parallel programming enviro...