With the consideration of low standby leakage in nanoscale CMOS processes, a new 2×VDD-tolerant ESD clamp circuit was presented in this paper. The new ESD clamp circuit had a high-voltage-tolerant ESD detection circuit to improve the turn-on efficiency of the silicon-controlled-rectifier-based (SCRbased) ESD device. This design had been successfully verified in a 65-nm CMOS process. The leakage...

Wide-range level shifters play critical roles in ultralow-voltage circuits and systems. In this paper level shifter circuits that are capable of converting subthreshold to above threshold signal levels are presented. Level shifters are designed using current mirrors. The circuit has a distinctive current generation scheme using a logic error correction circuit that works by detecting the input ...

A new current-source control technique is proposed to design a low-power high-speed multiplevalued current-mode (MVCM) integrated circuit in a low supply voltage. The use of a di erential logic circuit (DLC) with a pair of dual-rail inputs makes the input voltage swing small, which results in a high driving capability at a lower supply voltage, while having large static power dissipation. In th...

This paper presents a voltage based CMOS winner-take-all (WTA) circuit for analog voltage signals. The WTA circuit is based on a winner follower and wide-range transconductance amplifiers. The voltage based design uses capacitive storage for low power consumption. The circuit is modularized and its layout size is a linear function of the number of inputs. This makes the circuit easy to be imple...

This paper presents a second order voltage mode quadrature sinusoidal oscillator using a recently reported active building block, namely the differential voltage current controlled conveyor transconductance amplifier. The circuit proposed here employs single differential voltage current controlled conveyor transconductance amplifier, two grounded resistors and two grounded capacitors. The use o...

An ultra-low-power constant charge injector (CCI) circuit is presented for wirelessly-powered electro-acupuncture (EA). The CCI adopts adaptive pulse-width and frequency-drift (APF) calibration loop that not only accommodates to body impedance variation (BIV) of 100-200k but also is tolerable to frequency-drift. The proposed 5Hz current starving clock generator combined with sub-Vth reference ...

A new current-mode squaring circuit that can be used as a basic building block in analog signal processing systems is proposed. The design is based on MOS operating in the subthreshold region to assure low voltage and low power consumption. The performance of the design was confirmed by HSPICE simulation in 0.18m CMOS process. The circuit is operated by ±0.7V supply voltage and consumes 0.2μW ...

Design of a 3.3V comaptible 2.5V TTL-toCMOS bidirectional I/O buffer is proposed. Gate oxide protectiom was implemented without active voltage degradation, which reduces static and dynamic current levels and improves noise immunity for the low voltage circuit of this kind. Fast removal of stored charge further improve gate oxide protection and circuit recovery from overvoltage condition. Circui...

In this paper, a new circuit scheme is proposed to reduce the power consumption of dynamic circuits. In the proposed circuit, an NMOS keeper transistor is used to maintain the voltage level in the output node against charge sharing, leakage current and noise sources. Using the proposed keeper scheme, the voltage swing on the dynamic node is lowered to reduce the power consumption of wide fan-in...