Information on false paths in a circuit is useful for design and test. Since identification of the false paths at gate level is hard, several methods using high-level design information have been proposed. These methods are effective only if the correspondence between paths at register transfer level (RTL) and at gate level can be established. Until now, the correspondence has been established ...

This paper describes a low power threshold logic-gate based on a capacitive input, charge recycling differential sense amplifier latch. The gate is shown to have low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations. This is followed by the main result, which is the development of a novel, low depth, carry lookahead additi...

Several analytical methods for estimating the subthreshold and gate oxide leakage currents in CMOS circuits have been presented in the literature. However, such currents are strongly dependent on the fabrication process targeted, and the methods present different prediction data accuracy according to the profile of logic gates, in terms of transistor arrangements, stacked devices, and gate sizi...

In the recent scenario of microelectronic industry, the reversible logic is considered as the burgeonic technology for digital circuit designing. It deals with the aim to generate digital circuits with zero power loss characteristics. Optical computing, Nanotechnology, Low power CMOS design and Digital Signal Processing (DSP) processors are leading areas of development with the concept of rever...

Short Abstract Most industrial digital circuits contain three-state elements besides pure logic gates. We like to presents a gate delay fault test generator for sequential circuits with standard scan design that can handle three-state elements like bus drivers, transmission gates and pulled busses. The delay test pattern generator is based on a well-proved stuck-at test pattern generator that w...

A method to integrate an (in principle) unlimited number of molecular logic gates to construct complex circuits is presented. Logic circuits, such as half- or full-adders, can be reinterpreted by using the functional completeness of the implication function (IMP) and the trivial FALSE operation. The molecular gate IMP is represented by a fluorescent boronic acid sugar probe. An external wiring ...

We offer an alternative to the conventional network formulation of quantum computing. We advance the analog approach to quantum logic gate/circuit construction. As an illustration, we consider the spatially extended NOT gate as the first step in the development of this approach. We derive an explicit form of the interaction Hamiltonian corresponding to this gate and analyze its properties. We a...

After a short review of the state-of-the-art, a new low-power differential threshold logic gate is introduced: split-precharge differential noiseimmune threshold logic (SPD-NTL). It is based on combining the split-level precharge differential logic, with a technique for enhancing the noise immunity of threshold logic gates: noise suppression logic. Another idea included in the design of the SPD...

In this review paper we reviewed that the Programmable reversible logic is emerging as a prospective logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on circuit heat generation. Many researchers provide advances in reversible logic using and quantum computer algorithms allow for improved computer architecture and arithmetic logic unit desi...

Field programmable gate arrays (FPGAs) are increasingly used as the computing platform for fast and energy efficient execution of recognition, mining, and search applications. Approximate computing is one promising method for achieving energy efficiency. Compared with most prior works on approximate computing, which target approximate processors and arithmetic blocks. Hybrid configurable logic ...