Field-Programmable Gate Arrays (FPGAs) and Single-Instruction Multiple-Data (SIMD) processing arrays share many architectural features. In both architectures, an array of simple, ne-grained logic elements is employed to provide high-speed, customizable, bit-wise computation. In this paper, we present a uni ed computational array model which encompasses both FPGAs and SIMD arrays. Within this fr...

The paper studies the role of neutrality in the tness landscapes associated with the evolutionary design of digital circuits and particularly the three-bit binary multiplier. For the purpose of the study, digital circuits are evolved extrinsically on an array of logic cells. To evolve on an array of cells, a genotype-phenotype mapping has been devised by which neutrality can be embedded in the ...

Enhancing undergraduate and graduate curriculum to include state-of-the-art tools and techniques deserves utmost importance in this fast pacedworld of engine ering and technological growth. Design, the art of applying one's knowledge and exp erienc e to the solution of real problems is what makes engineering an exciting and rewarding career. In this pap er,exp erience from teaching a senior lev...

A Product Line Potential Analysis enables us to make a quick decision as to whether the product line approach (PLA) is suitable for a given set of products and target market. The PLA framework offers no support for this as yet. A Product Line Potential Analysis is executed in a half-day workshop. A structured interview based on a questionnaire examines products, software, markets, and customers...

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix Zusammenfassung . . . . . . . . . . . . . . . . . . . . . . . . . . . xi

Programmable logic arrays (PLAs) are being used to implement complex multivalued logic (MVL) circuits. In this paper we introduce three new current-mode CMOS MVL-PLA structures for the implementation of MVL functions. These PLA structures use four current-mode CMOS building blocks namely, cycle, min, tsum and constants. Comparison between the introduced architectures is made based on their resp...

Mixed-type documents include text, drawings and graphics regions. It is obvious that a technique that can reduce the number of the gray-levels in accordance with the type of each document region could be important for many document applications, such as storage, transmission and recognition. To solve this problem, this paper proposes a new method, called the document multithresholding technique...

Several measurements are used to describe the behavior of a diabetic patient’s blood glucose. We describe a new, wavelet-based algorithm that indicates a new measurement called a PLA index could be used to quantify the variability or predictability of blood glucose. This wavelet-based approach emphasizes the shape of a blood glucose graph. Using continuous glucose monitors (CGMs), this measurem...

This paper describes the synthesis of dynamic differential logic to increase the resistance of FPGAs against Differential Power Analysis. Compared with an existing technique, it saves more than a factor 2 in slice utilization. Experimental results indicate that a secure version of the AES algorithm can now be implemented with a mere doubling of the slice utilization when compared with a normal ...

This paper presents a summary of a study into the possibility of integration of eld programmable logic and optoelectronic devices. Our primary motivation is a recent development of dynamically recon-gurable FPGAs (DR FPGAs), for which the reconnguration time has a mandatory impact on their performance. We review limitations of DR FPGAs, discuss advantages of optically reconngurable logic, inves...