Design and experimental validation of a simple photonic phase-lockedloop (PPLL) linear phase demodulator employing a novel attenuating counter propagating (ACP) in-loop phase modulator are presented. The ACP in-loop phase modulator is free of propagation delay, allowing stable operation of the PPLL with large gain. Highly linear optical phase demodulation was observed and the measured spurious ...

This paper presents a review of phase locked loop (PLL) techniques. The different types of phase detector, loop filter and oscillators are discussed. It alleviates the problems associated with the classical analog PLL. Linear PLL, Digital PLL and All digital PLL models are implemented in Simulink Simulation results in Simulink gives the performance overview of the three types of PLL. Keywords— ...

Among the various faults of power transformers, winding are particularly common. It is known that short-circuit parameters can reflect condition, so on-line identification great significance for monitoring transformer health. An instantaneous phasor extraction method based on Second-Order Generalised Integrator Frequency-Locked Loop introduced, and then an algorithm proposed. In this algorithm,...

This research addresses the special requirements of phase locked loops (PLLs) for a typical application with FACTS elements. A new PLL system that uses adaptation algorithms is developed with the aim of improving speed of responses, robustness to AC voltage depressions, and harmonic rejection. The adaptive PLL consists of the three control units that individually control frequency, phase angle,...

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This paper describes the design and implementation of a current-mode phase-locked loop (PLL) using static and dynamic (log-domain) translinear circuits. The loop is fully tuneable, with independent control of center frequency and loop bandwidth. The loop employs a recently proposed current-mode “log-domain” oscillator in a classical PLL topology to obtain these features. The PLL has been fabric...

The duty-cycle of a clock, within the VLSI IC, is liable to be changed when the clock passes through several buffer stages in the multistage clock buffer design. The pulse-width may be changed due to unbalance of the p and n MOS transistors in the long CMOS buffer. This paper describes a delay locked loop with double edge synchronization mainly used in a clock alignment process. SPICE simulatio...

Introduction Phase-locked loops (PLLs) are one of the basic building blocks in modern electronic systems. They have been widely used in communications, multimedia and many other applications. The theory and mathematical models used to describe PLLs are of two types: linear and nonlinear. Nonlinear theory is often complicated and difficult to deal with in real-world designs. Analog PLLs have bee...

active filters have proven to be more effective than passive techniques to improve power quality and to solve harmonic and power factor problems due to nonlinear loads. this paper proposes a control scheme based on the instantaneous active and reactive power. the inverter of this active filter is a three-phase, two-level converter. space vector technique is used as modulators and pattern genera...

This paper demonstrates the use of a spreadsheet in exploring non-linear difference equations that describe digital control systems used in radio engineering, communication and computer architecture. These systems, being the focus of intensive studies of mathematicians and engineers over the last 40 years, may exhibit extremely complicated behavior interpreted in contemporary terms as transitio...