In this paper, a 1 V UWB LNA in TSMC 0.13 um CMOS process technology is designed. The power consumption is only 7.6 mW. By employing RLC peaking, high-frequency poles are moved outside of the 3.1-10.6 GHz band of interest, and a flat power gain and an excellent phase linearity are achieved. By applying DC voltage to the bulk of transistors, a low voltage LNA is accomplished. The proposed LNA is...

BACKGROUND Real-time assays for Yellow fever virus (YFV) would help to improve acute diagnostics in outbreak investigations. OBJECTIVES To develop a real-time assay for YFV able to detect African and South American strains. STUDY DESIGN Three short probe (14-18 nt) formats were compared and a plasmid-transcribed RNA standard was used to test the performance of the assays. Additionally the n...

This work presents the design of an inductively source degenerated CMOS differential common source cascode Low Noise Amplifier (LNA) operating at 2 GHz frequency. An inductor is added at the drain of the main transistor to reduce the noise contribution of the cascode transistors. Another inductor connected at the gate of the cascode transistor and capacitive cross-coupling are strategically com...

A fully integrated CMOS wideband Low Noise Amplifier (LNA) operating over 2.3–7 GHz is designed and fabricated using a 0.18 μm CMOS process. The proposed structure is a common sourcecommon source (CS-CS) cascode amplifier with a coupling capacitor. It realizes both low voltage drop at load resistor (Rload) and high gain over 2.3–7 GHz with simultaneous noise and input matching and low power con...

Increasing demands of portable wireless devices have motivated the development of CMOS radio frequency integrated circuits (RFIC). In wireless system Low Noise Amplifier is the first stage of any RF Receiver design. Performance of RF receiver mainly depends on the effectiveness of LNA. The main objective of the LNA design is to get good gain with minimum noise generation for the entire operatin...

The objective of this paper is to investigate a ultra-wideband (UWB) low noise amplifier (LNA) by utilizing a two-stage cascade circuit schematic associated with inductive-series peaking technique, which can improve the bandwidth in the 3 10 GHz microwave monolithic integrated circuit (MMIC). The proposed UWB LNA amplifier was implemented with both co-planer waveguide (CPW) layout and 0.15 μm G...

The design of antisense oligonucleotides containing locked nucleic acids (LNA) was optimized and compared to intensively studied DNA oligonucleotides, phosphorothioates and 2'-O-methyl gapmers. In contradiction to the literature, a stretch of seven or eight DNA monomers in the center of a chimeric DNA/LNA oligonucleotide is necessary for full activation of RNase H to cleave the target RNA. For ...

A fully integrated 5.5 GHz high-linearity low noise amplifier (LNA) using post-linearization technique, implemented in a 0.18μm RF CMOS technology, is demonstrated. The proposed technique adopts an additional folded diode with a parallel RC circuit as an intermodulation distortion (IMD) sinker. The proposed LNA not only achieves high linearity, but also minimizes the degradation of gain, noise ...

The effect of gate – drain/source underlap (Lun) on a narrow band LNA performance has been studied, in 30 nm FinFET using device and mixed mode simulations. Studies are sssssdone by maintaining and not maintaining the leakage current (Ioff) and threshold voltage (Vth) of the various devices. LNA circuit with two transistors in a cascode arrangement is constructed and the input impedance, gain a...

n this paper the Low Noise Amplifier (LNA) operating with a centre frequency of 1.5 GHz is designed using 0.25μm CMOS technology. The Designed FB-LNA uses a stagger-tuning technique. A current-reused architecture is employed to decrease the power consumption using an input common-gate stage, common-gate lownoise amplifier (CGLNA) exhibits a relatively high noise figure (NF) at low operating fre...