In this paper, an effective T-gate with Drain-Field-Plate (TGDFP) technology is used in GaN-based HEMT for high breakdown voltage of 500V and drain current of 540mA/mm. Silvaco TCAD simulation showed that normally-off TGDFP HEMT with recessed gate length of 0.5μm exhibited high threshold voltage up to +1V and transconductance of 140mS/mm along with frequency operation in Sband (∼3GHz). The prop...

This paper introduces performance aspects as a new optimization criteria when generating Gate Matrix Layouts. A new layout model is presented that limits the amount o f parasitic capacitance in signal paths and the resistance in power supply lines. The performance considerations are combined with a new layout s-trate g y that improves circuit performance with little or no area penalty. A n Auto...

Low-field mobilities for electrons in the channel of an Al0.15Ga0.85N/GaN heterostructure field-effect transistor are derived from direct current transistor characteristics. The dependencies of mobility on gate bias, sheet carrier concentration, and temperature are obtained. For negative gate bias voltages, mobility is found to increase monotonically with increasing sheet carrier concentration,...

This paper introduces performance aspects as a new optimization criteria when generating Gate Matrix Layouts. A new layout model is presented that limits the amount o f parasitic capacitance in signal paths and the resistance in power supply lines. The performance considerations are combined with a new layout s-trate g y that improves circuit performance with little or no area penalty. A n Auto...

Layered 2D semiconductors have been widely exploited in photodetectors due to their excellent electronic and optoelectronic properties. To improve performance, photogating, photoconductive, photovoltaic, photothermoelectric, other effects used phototransistors photodiodes made with or hybrid structures. However, it is difficult achieve the desired high responsivity linear photoresponse simultan...

Reversible logic has become one in all the promising analysis directions in low power dissipating circuit style within the past few years and has found its applications in low power CMOS style, cryptography, digital signal process, optical scientific discipline and engineering. This paper presents a quantum price economical reversible full adder gate and Reversible Decoder in engineering. This ...

The impact of gate oxide degradation of a single pMOSFET on the performance of the CMOS NOR logic circuit has been examined using a switch matrix technique. A constant voltage stress of -4.0V was used to induce a low level of degradation to the 2.0nm gate oxide of the pMOSFET. Characteristics of the CMOS NOR logic circuit following gate oxide degradation are analyzed in both the DC and V-t doma...

A layered graph is a connected graph whose vertices are partitioned into sets L0 = {s}, L1, L2, ..., and whose edges, which have nonnegative integral weights, run between consecutive layers. Its width is max{|Li|}. In the on-line layered graph traversal problem, a searcher starts at s in a layered graph of unknown width and tries to reach a target vertex t; however, the vertices in layer i and ...

BACKGROUND AND PURPOSE A susceptibility vessel sign (SVS) on 1.5-tesla (T)-T2*-weighted images may predict cardioembolism. It has also been detected in patients with large artery atherosclerosis. In patients with major vessel occlusion, the SVS was comprised 2 layers on 3T-T2*-weighted images. We assessed the efficacy of 2-layered SVS on 3T-T2*-weighted imaging scans for predicting cardioemboli...