and work developed by the undergraduate student Elísio Varela among other researchers. Also, aiming the architecture implementation of the intracortical prosthesis in VLSI circuits, it includes the written contribution and results of.

OF THE DISSERTATION Process Variation Aware Interconnect Simulation and Optimization in VLSI Design

Date approved by Chairman ________________________ iii ACKNOWLEDGMENT Many people have made this opportunity possible. Above all, this work could not have been completed without Dr. Martin Brooke's support, guidance, patience, resourcefulness, and humor.

This paper describes the ideas and philosophy behind a new compact model (CM) for deep-submicron MOSFETs, called Xsim, which has been developed from scratch over the past few years. Similarities to and differences from existing popular models are pointed out. The opinions on many controversial debates in the CM field are given. The ultimate goal of the CM development in the context of technolog...

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Paschalis et al. in [12] have given a structured method to design TSC m-out-of-2m code checkers suitable for VLSI implementation. In this correspondence we give sufficient conditions so that the method given in [12] can be used to design checkers for classes of m-outof-n codes with n * 2m.

In order to achieve multi-GHz operation frequency for VLSI design, clock networks need to be designed in a very elaborated manner and be able to deliver prescribed useful skews rather than merely zero-skew. Although traditional zero-skew clock routing methods can be extended directly to prescribed skews, they tend to result in excessive wirelength as the differences among delay-targets for cloc...

The field of neuromorphic engineering is a relatively new one. In this paper we introduce the basic concepts underlying neuromorphic engineering and point out how this type of research could be exploited for industrial applications. We describe some of the circuits commonly used in neuromorphic analog VLSI chips and present examples of neuromorphic systems, containing vision chips for extractin...

This paper describes a new algorithm for the extraction of the critical area for opens. The presented algorithm allows for the analysis of large IC’s and non-Manhattan geometry. Concept of the contact/via contacting regions is proposed and its relevance is discussed. Illustrative examples of the proposed algorithm are presented.