This paper enumerates low power, high speed design of TSPC (True Single Phase Clocking) D flip-flop having less number of transistors. This technique allows circuit to achieve lowest power consumption with minimum transistor count. Design of low power device is now an essential field of research due to increase in demand of portable devices. In the circuit as the scaling increase the leakage po...

This paper presents a method of design the counter using sequential system based on synchronous techniques. For the design the counter, first of all, we derive switching algebras and their operations. Also, we obtain the next-state functions, flip-flop excitations and their input functions from the flip-flop. Then, we propose the algorithm which is a method of implementation of the synchronous ...

Radiation effects account for increasing soft error occurrences in deep submicron circuits. A method for calculating an upper bound for the width of an erroneous pulse that may reach a flip flop or a primary output is presented. This is required in order to determine pulse removal (PR) circuit characteristics for error correction at each flip flop or primary output side. Key-Words: Soft errors,...

In this paper we propose, experimentally realize and study possible applications of a new type of logic element: random flip-flop. By definition it operates similarly to a conventional flipflop except that it functions with probability of 1/2 otherwise it does nothing. We demonstrate one practical realization of the random flip-flop based on optical quantum random number generator and discuss p...

In this paper a technique is proposed to reduce the power consumption in clock distribution networks. Power has become a major issue in most VLSI designs. Power distribution in VLSI differs from product to product. However it is interesting to note that clock system and logic part itself consume most of total chip power. In practise a large portion of clock distribution network (CDN)s and flip ...

Alamethicin is a hydrophobic antibiotic peptide 20 amino acids in length. It is predominantly helical and partitions into lipid bilayers mostly in transmembrane orientations. The rate of the peptide transverse diffusion (flip-flop) in palmitoyl-oleyl-phosphatidylcholine vesicles has been measured recently and the results suggest that it involves an energy barrier, presumably due to the free ene...

The power consumption of modern highly complex chips during scan test is significantly higher than the consumed functional mode. This leads to substantial heat dissipation, excessive IR drop, and unrealistic timing failures integrated circuits (ICs) under test. In this brief, a ByPassable Scan Data Retention Flip-Flop (BPS-DRFF) proposed for low-power IC flip-flop contains two secondary latches...

A Delay (D) flip-flop is an edge triggering device. A high speed, low power consumption, positive edge triggered conventional Delay (D) flip-flop can be designed for increasing the speed of counter in Phase locked loop, using 32nm CMOS technology. The conventional D flip-flop has higher operating frequencies but it features static power dissipation. The designed counter can be used in the divid...

In this paper, a low power single edge triggered D flip-flop is presented by using True Single Phase Clocked technique (TSPC). The proposed design overcomes the problem of race condition at the output caused by clock pulses. This technique uses single phase clock pulse and it has less number of transistors. All the circuits are designed and simulated using Cadence® Virtuoso® Design Environment ...

Intact platelets do not show procoagulant phospholipids on their exterior. These phospholipids are located at the inside leaf of the bilayer membrane. They become available by (a) disrupture of the platelets (mechanical, osmotical etc.), (b) by a mechanism specific for the platelets, that we call the membrane flip-flop. Membrane flip-flop translocates procoagulant phospholipids (mainly phosphat...