We report on the defect generation under constant voltage stress in La2O3/HfO2 gate stacks grown on Germanium (001) substrates by molecular beam deposition utilizing a stress and sense technique. A voltage range from 0.5V up to 2.4V was used for the measurements. At low applied gate voltages, the stress induced current decrease could be explained by a field lowering model due to charge trapping...

In this paper, an effective T-gate with Drain-Field-Plate (TGDFP) technology is used in GaN-based HEMT for high breakdown voltage of 500V and drain current of 540mA/mm. Silvaco TCAD simulation showed that normally-off TGDFP HEMT with recessed gate length of 0.5μm exhibited high threshold voltage up to +1V and transconductance of 140mS/mm along with frequency operation in Sband (∼3GHz). The prop...

Random telegraph signals corresponding to activated charge traps were observed with liquid-gated CNT FETs. The high signal-to-noise ratio that we observe demonstrates that single electron charge sensing is possible with CNT FETs in liquids at room temperature. We have characterized the gate-voltage dependence of the random telegraph signals and compared to theoretical predictions. The gate-volt...

We develop a simple method to fabricate the two-stacked graphene monolayers and investigate the electronic transport in such a system. The independence of the two graphene monolayers gives rise to the asymmetric resistance-gate voltage curves and an eight-fold degeneracy of Landau level. The position of the maximum resistance of the transfer curves shifts towards higher gate voltage with increa...

An availability and a reliability prediction has been made for a high-voltage direct-current (HVDC) module of VSC (Voltage Source Converter) containing DC/DC converter, gate driver, capacitor and insulated gate bipolar transistors (IGBT). This prediction was made using published failure rates for the electronic equipment. The purpose of this prediction is to determinate the additional module re...

Graphene field effect transistors commonly comprise graphene flakes lying on SiO(2) surfaces. The gate-voltage dependent conductance shows hysteresis depending on the gate sweeping rate/range. It is shown here that the transistors exhibit two different kinds of hysteresis in their electrical characteristics. Charge transfer causes a positive shift in the gate voltage of the minimum conductance,...

High-performance inversion-type enhancementmode n-channel In0.53Ga0.47As MOSFETs with atomiclayer-deposited (ALD) Al2O3 as gate dielectric are demonstrated. The ALD process on III–V compound semiconductors enables the formation of high-quality gate oxides and unpinning of Fermi level on compound semiconductors in general. A 0.5-μm gate-length MOSFET with an Al2O3 gate oxide thickness of 8 nm sh...

We propose a novel sloped dielectric geometry in graphene as a band engineering method for widening the depletion region and increasing the electrical rectification effect in graphene pn junctions. Enhanced current-rectification was achieved in a bilayer graphene with a sloped dielectric top gate and a normal back gate. A bias was applied to the top gate to induce a spatially modulated and slop...

In this study, we synthesized an organic electrochemical transistor (OECT) using dielectrophoresis of a carbon nanotube-Nafion (CNT-Nafion) suspension. Dielectrophoretically aligned nanowires formed a one-dimensional submicron bundle between triangular electrodes. The CNT-Nafion composite nanowire bundles showed p-type semiconductor characteristics. The drain-source current decreased with incre...

Ultrathin (approximately three quintuple layer) field-effect transistors (FETs) of topological insulator Bi(2)Se(3) are prepared by mechanical exfoliation on 300 nm SiO(2)/Si susbtrates. Temperature- and gate-voltage-dependent conductance measurements show that ultrathin Bi(2)Se(3) FETs are n-type and have a clear OFF state at negative gate voltage, with activated temperature-dependent conducta...