In this paper, we proposed a 2-D analytical model for electrical characteristics such as surface potential, electric field and drain current of Silicon-on-Insulator Tunnel Field Effect Transistor (SOI TFETs) with a SiO2/High-k stacked gate-oxide structure. By using superposition principle with suitable boundary conditions, the Poisson’s equation has been solved to model the channel r...

We report dual-gate modulation of topological insulator field-effect transistors (TI FETs) made on Bi2Te3 thin flakes with integration of atomic-layer-deposited (ALD) Al2O3 high-k dielectric. Atomic force microscopy study shows that ALD Al2O3 is uniformly grown on this layer-structured channel material. Electrical characterization reveals that the right selection of ALD precursors and the relat...

This paper describes the design and optimization of gate-all-around (GAA) MOSFETs structures. The optimum value of Fin width and Fin height are investigated for superior subthreshold behavior. Also the performance of Fin shaped GAA with gate oxide HfO2 are simulated and compared with conventional gate oxide SiO2 for the same structure. As a result, it was observed that the GAA with high K diele...

The gate-oxide (aka gate tunneling or gate) leakage due to quantum-mechanical direct tunneling of carriers across the gate dielectric of a device is a major source power dissipation for sub-65nm CMOS circuits. In this paper a high-level (aka architecture) synthesis algorithm is presented that simultaneously schedules operations and binds to modules for gate leakage optimization. The algorithm u...

Graphene field effect transistors with an Al2O3 gate dielectric are fabricated on H-intercalated bilayer graphene grown on semi-insulating 4H-SiC by chemical vapour deposition. DC measurements of the gate voltage vg versus the drain current id reveal a severe hysteresis of clockwise orientation. A capacitive model is used to derive the relationship between the applied gate voltage and the Fermi...

Our ability of controlling the growth and interfaces of thin dielectric films on III–V semiconductors by ultrahigh vacuum deposition has led to investigations of gate stacks containing rare earth oxides of Gd2O3 and Y2O3 as alternative high k gate dielectrics for Si. The abrupt interfaces achieved in these gate stacks have enabled the electrical, chemical, and structural studies to elucidate th...

A high-mobility (9000 cm2/V‚s) semiconducting single-walled nanotube transistor is used to construct a nonvolatile charge-storage memory element operating at room temperature. Charges are stored by application of a few volts across the silicon dioxide dielectric between nanotube and silicon substrate, and detected by threshold shift of the nanotube field-effect transistor. The high mobility of ...

The outstanding properties of SiO2 , which include high resistivity, excellent dielectric strength, a large band gap, a high melting point, and a native, low defect density interface with Si, are in large part responsible for enabling the microelectronics revolution. The Si/SiO2 interface, which forms the heart of the modern metal–oxide–semiconductor field effect transistor, the building block ...

Germanium (Ge) has gained great attention not only for future nanoelectronics but back-end of line (BEOL) compatible monolithic three-dimensional (M3D) integration recently. For high performance and low power devices, various high-k oxide/Ge gate stacks including ferroelectric oxides have been investigated. Here, we demonstrate atomic layer deposited (ALD) polycrystalline (p-) HfO <sub xmlns:mm...