Following the simple Programmable Logic Device (SPLD) and Field Programmable Gate Array (FPGA) generations a third generation of programmable logic technologies is now reaching the marketplace. These new architectures are driven by the move to system level integration and fast expanding markets such as networking and wireless communications which are not addressed adequately by mainstream FPGA'...

In this paper, a new method is introduced to implement chaotic generators based on the Henon map and Lorenz chaotic generators given by the state equations using the Field Programmable Gate Array (FPGA). The aim of this method is to increase the frequency of the chaotic generators. The new method is based on the MATLAB Software, Xilinx System Generator, Xilinx Alliance tools and Synplicity Synp...

The goal of this work is to fabricate robust, miniature, wireless sensor modules. These provide an enabling technology platform to conduct research in creating ambient systems, through implementing wireless sensor network applications. The approach taken is to partition the wireless sensor module into a series of layers with area 25mm x 25mm. This modular approach has resulted in the specificat...

This work reports a non-pipelined AES (Advanced Encrypted Standard) FPGA (Field Programmable Gate Array) architecture, with low resource requirements. The architecture is designed to work on CBC (Cipher Block Chaining) mode and achieves a throughput of 1.45 Gbps. This implementation is a module of a configuration library for a Cryptographic Reconfigurable Platform (CRP).

A test procedure for testing mainly the boundary scan cells, and testing partially the test access port controller in programmable logic devices, and field programmable gate array devices, is suggested. The test procedure involves; the configuration of programmable logic devices or field programmable gate array device, the application of test vectors, and finally the verification of the respons...

Adaptive Computing is a relatively new research area [1]. The main thrust of this research area so far has been on programmable/configurable hardware. Significant successes have been reported. The programmable gate array (FPGA) technology has matured producing very high-density gate arrays (~1 million gates) with lower configuration times. A variety of hardware platforms comprising of microproc...

This paper presents a clocking pipeline technique referred to as a single-pulse pipeline (PP-Pipeline) and applies it to the problem of mapping pipelined circuits to a Field Programmable Gate Array (FPGA). A PP-pipeline replicates the operation of asynchronous micropipelined control mechanisms using synchronous-orientated logic resources commonly found in FPGA devices. Consequently, circuits wi...

This paper proposes an approach to design a cost-eeective domain-speciic fault-tolerant computing architecture that can dynamically meet the fault tolerance requirements of applications and their performance requirements. The design is based on eld-programmable gate array technology.

In nature, localization is a very fundamental task for which natural evolution has come up with many powerful solutions. In technical applications, however, localization is still quite a challenge, since most ready-to-use systems are not satisfactory in terms of costs, resolution, and effective range. This paper proposes a new localization system that is largely inspired by auditory system of t...