With the dramatic increase in the number of transistors on a chip and the increasing needs for battery-powered applications, low-voltage circuit design techniques have been widely studied in recent year. However, these low supply voltage research efforts have been focused mainly on digital circuits, especially on high density memory circuits. Reported success in achieved high performance low vo...

We describe a floating-gate trimmed 14-bit 300-MS/s current-steered digital-to-analog converter (DAC) fabricated in 0.25and 0.18m CMOS logic processes. We trim the static integral nonlinearity to 0.3 least significant bits using analog charge stored on floating-gate pFETs. The DAC occupies 0.44 mm of die area, consumes 53 mW at 250 MHz, allows on-chip electrical trimming, and achieves better th...

We present a floating-gate based system for computing vector quantization (VQ), which is typically used for data compression and classification of signals to symbols. We present an architecture and resulting circuits which will enable direct programming / storage of weight vectors, as well as methods for adaptive VQ. We use an analog bump circuit to perform a continuous distance computation alo...

Undoped GaN-based metal-oxide-semiconductor high-electron-mobility-transistors MOS-HEMTs with atomic-layer-deposited Al2O3 gate dielectrics are fabricated with gate lengths from 1 μm up to 40 μm. With a two-dimensional numerical simulator, we report simulation results of the GaN-based MOS-HEMTs using field-dependent drift velocity model. A developed model, taking into account polarization-induc...

In this paper, we have developed a model of the tunneling current through a highdielectric stack in MOS capacitors with anisotropic masses. The transmittance was numerically calculated by employing a transfer matrix method and including longitudinal-transverse kinetic energy coupling which is represented by an electron phase velocity in the gate. The transmittance was then applied to calculate ...

this paper proposes a low voltage (±0.55v supply voltage) low power (44.65µw) high common mode rejection ratio (cmrr) differential amplifier (d.a.) with rail to rail input common mode range (icmr), constant transconductance (gm) and enhanced frequency performance. its high performance is obtained using a simple negative averaging method so that it cancels out the common mode input signals at th...

In this article threshold gates with hysteresis using neuron MOS (νMOS) are presented as basic elements in Null Convention Logic (NCL) circuits. NCL, which proposed by K. M. Fant and S. A. Branst, needs special gates having hysteresis, because NCL uses different ternary logic systems in computation phase and wiping phase of asynchronous behavior, respectively. To impliment the dinamic behavior,...

Nano-floating gate memory devices were fabricated on a flexible plastic substrate by a low-temperature fabrication process. The memory characteristics of ZnO-based thin-film transistors with Al nanoparticles embedded in the gate oxides were investigated in this study. Their electron mobility was found to be 0.18 cm(2)/V·s and their on/off ratio was in the range of 10(4)-10(5). The threshold vol...

A floating gate charge-sharing circuit that can be electrically programmed for precise positive and negative voltage changes, and can be implemented in a standard CMOS VLSI process is presented. With the advantage of its longterm charge-retention, the floating gate charge-sharing circuit is suitable for providing a compact, non-volatile and high-precision analog trimming method to trim the offs...

PREFACE While the digital world frantically pursues ever-faster clock speeds to satisfy demanding signal processing applications, a quiet revolution in analog computing has been brewing, which promises to do more with less — more sophisticated signal processing delivered at less power in a smaller space. Novel application of a digital memory technology, the floating-gate MOS-FET (used in EEPROM...