In Analog to digital convertor design converter, high speed comparator influences the overall performance of Flash/Pipeline Analog to Digital Converter (ADC) directly. This paper presents the schematic design of a CMOS comparator with high speed, low noise and low power dissipation. A schematic design of this comparator is given with 0.18μm TSMC Technology and simulated in cadence environment. ...

A high resolution Time Correlated Single Photon Counting (TCSPC) image sensor based on sample and hold Time to Amplitude Converter (TAC)pixels and a global ramp voltage is presented. The 256× 256 array achieves an 8 μm Pixel Pitch (PP), 19.63% Fill Factor (FF), output voltage range (0.7V) and time jitter of 368 ps at 10 fps employing an off-chip 14-bit differential Analogue to Digital Converter...

background diffusion-weighted imaging (dwi) is a form of magnetic resonance imaging (mri) based on measuring the random brownian motion of water molecules within the biological tissues and is particularly useful in tumor characterization. objectives the purpose of this study was to evaluate the diagnostic value of dw mri and the apparent diffusion coefficient (adc) for preoperative grading of a...

Successive-approximation-register (SAR) analog-to-digital converters (ADCs) represent the majority of the ADC market for mediumto high-resolution ADCs. SAR ADCs provide up to 5Msps sampling rates with resolutions from 8 to 18 bits. The SAR architecture allows for high-performance, lowpower ADCs to be packaged in small form factors for today's demanding applications. This paper will explain how ...

Abstrac t-A flash Analog to Digital Converter (ADC) at 3 Giga samples per second (GS/s) was developed using QUBIC4X which is a 0.25 um SiGeC process from NXP Semiconductors. The ADC has a bandwidth close to 1.2 GHz with a resolution of 6-bit. The full design employs a differential structure. The ADC uses a parallel architecture consisting of the following components: track and hold, comparators...

This paper describes a new analog-to-digital converter based on the traditional dual-slope ADC operation. With a small modification to the discharging phase of the dual-slope ADC, first-order quantization noise shaping is achieved. This quantizer is used in a second-order loop filter and results in an overall third-order quantization noise shaping. To remove the need for any extra active elemen...

Successive-approximation-register (SAR) analog-to-digital converters (ADCs) represent the majority of the ADC market for mediumto high-resolution ADCs. SAR ADCs provide up to 5Msps sampling rates with resolutions from 8 to 18 bits. The SAR architecture allows for high-performance, low-power ADCs to be packaged in small form factors for today's demanding applications. This paper will explain how...