A recently proposed method obtains path delay fault coverages by estimating the count of the number of tested faults instead of actually enumerating them. The estimate become pessimistic when several paths share a set of lines. In this communication, we present a continuum of improved approximations for the counting method, approaching exact fault simulation, to allow trade-o s between accuracy...

A fault management dispatcher training simulator for large-scale Distribution Automation System (TDAS) is developed to train operators in distribution control center. This simulator is composed of independent simulation server and operator consoles and can be used for network analysis, network operation, fault management and evaluation. TDAS DB is duplicated online to the simulation server keep...

Influence of distributed generation systems in the distribution systems can increase the level of short-circuit current. The effectiveness of distributed generation systems is affected by the size, location, type of distributed generation systems technology, and the methods of connecting to distribution systems. Wind turbine system is the examples of distributed generation source. Not only does...

This paper presents a methodology for designing a fault-tolerant control (FTC) system for linear parameter varying (LPV) systems subject to actuator saturation fault. The FTC system is designed using linear matrix inequality (LMI) and model estimation techniques. The FTC system consists of a nominal control, fault diagnostic, and fault accommodation schemes. These schemes are designed to achiev...

Although electrical simulation has become a vital tool in the design process of memory devices, memory testing has not yet been able to employ electrical simulation as an integral part of the test generation and optimization process. This is due to the exponential complexity of the simulation-based fault analysis, a complexity that made such an analysis impractical. This paper describes new met...

A Computer-Aided-Test (CAT) platform has been integrated in the Cadence Design Framework Environment for the evaluation of analogue/mixed-signal/RF Built-In-Self-Test (BIST) techniques. It comprises tools for statistical modelling of circuit performances, fault simulation, test generation and test optimization. The fault modelling and fault injection tools are simulator-independent, thus they a...

Testing has become an important design step now days in digital circuit. A gate level fault simulation environment based on realistic fault models has been presented in this paper. A Genetic Algorithm (GA) is proposed which allows having fault simulation with conditional execution of test vector under 2 phase scheme. By using this approach a random search of test vectors is possible without bei...

The increasing penetration of inverter-based distributed generations (DGs) significantly affects the fault characteristics of distribution networks. Fault analysis is a keystone for suitable protection scheme design. This paper presents the modelling methodology for distribution networks with inverter-based DGs and performs fault simulation based on the model. Firstly, a single inverter-based D...

This paper presents the versatility of our fault simulator in handling different fault models by adding new activity functions such as n-terminal bridge faults. We use our TUFTsim simulator, which is based on concurrent simulation algorithms to efficiently fault simulate large networks, and the Multiple List Traversal mechanism handles the propagation of concurrent elements through the topology...

A new method for parametric defect modelling is developed for calculating the conditions for activating physical defects in the modules (for example, in library components) of digital circuits. The method affords for the first time the possibility to handle the defects which increase the number of states in the circuit. By using the concept of functional faults, the new method of defect modelli...