The paper presents a method for testing a system-on-achip by using a compressed representation of the patterns on an external tester. The patterns for a certain core under test are decompressed by reusing scan chains of cores idle during that time. The method only requires a few additional gates in the wrapper, while the mission logic is untouched. Storage and bandwidth requirements for the ATE...

Recently, Larrabee proposed a sequential test generation algorithm for combinational circuits based on boolean satisfiability and presented results on benchmark circuits in support of the viability of this approach. Parallel implementations of test generation algorithms are attractive in view of the known difficulty (NP-completeness) of the problem. In this paper we suggest parallel versions of...

This paper discusses the technique for modeling a test generation problem using neural networks. Through examples, it illustrates the representation of a digital circuit as a hopfield network; the translation of faults to the same and the generation of test vectors for it. The results that have been reported, clearly indicate the advantage in using it as a means of parallelizing the test genera...

Optirnized locally exlzaustive test patterti yetietators bused on linear sunis promise a low overhead, bur ha\,e an irregular structure. The puper presents a new 0180t.ithm able to compute the linear sunis fo r real circuiis up to several h i d r e d s of inputs arid outpurs. The idea is to substitute a strategy of introducing fresh variables irito an array of sums fo r the former linear indepe...

This paper presents an implicit methodology that constrains a test pattern generator to identify test sequences which can be reproduced by cellular automata (CA). The so identiied CA can be synthesized as an autonomous-nite state machine and can be attached to the inputs of a circuit under test (e.g., a controller). In this way, the circuit under test preserves its integrity and its performance...

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This work extends a general method used to test classical circuits to quantum circuits. Gate internal errors are address using a discrete fault model. Fault models to represent unwanted nearest neighbor entanglement as well as unwanted qubit rotation are presented. When witnessed, the faults we model are probabilistic, but there is a set of tests with the highest probability of detecting a disc...

Due to the rapidly growing size of integrated circuits, there is a need for new algorithms for Automatic Test Pattern Generation (ATPG). While classical algorithms reach their limit, there have been recent advances in algorithms to solve Boolean Satisfiability (SAT). Because Boolean SAT solvers are working on Conjunctive Normal Forms (CNF), the problem has to be transformed. During transformati...

Digital circuits complexity and density are increasing and at the same time it should have more quality and reliability. It leads with high test costs and makes the validation more complex. The main aim is to develop a complete behavioral fault simulation and automatic test pattern generation (ATPG) system for digital circuits modeled in verilog and VHDL. An integrated Automatic Test Generation...

Automated test generation for object-oriented programs is an essential and yet a difficult task. Many automated test generation approaches produce test cases entirely from the program under test, without considering useful information from already created test cases. This paper presents an approach to regenerate test cases via exploiting frequently-used method call sequences from test repositor...