In this paper I will discuss the feasibility of an implementation of an algorithm containing a Deep Convolutional Neural Network for feature extraction, and softmax regression for feature classification, for the purpose of real-time lane detection on an embedded platform containing a multi-core Digital Signal Processor (DSP). I will explore the merits of using fixed point and floating point ari...

In this fast computing era, most of the embedded system requires more computing power to complete the complex function/ task at the lesser amount of time. One way to achieve this is by boosting up the processor performance which allows processor core to run faster. This paper presents a novel technique of increasing the performance by parallel HPRC (High Performance Reconfigurable Computing) in...

The digital band-pass filters used in the system and the DSP algorithm realizing the FM discriminator were designed using Matlab [3]. The filter coefficients and discriminator algorithm are incorporated in a program running on the DSP board. The DSP board samples the signal emitted by the ground-based radio navigation aid and processes the sampled data to obtain ILS and VOR information. The sam...

Title of dissertation: DATAFLOW INTEGRATION AND SIMULATION TECHNIQUES FOR DSP SYSTEM DESIGN TOOLS Chia-Jui Hsu Doctor of Philosophy, 2007 Dissertation directed by: Professor Shuvra S. Bhattacharyya Department of Electrical and Computer Engineering System-level modeling, simulation, and synthesis using dataflow models of computation are widespread in electronic design automation (EDA) tools for ...

This paper presents a feasibility study of applying a legacy reconfigurable single scalar DSP processor to media processing. The latest video compression standard H.264 was adopted as target application. First, a pure software H.264 decoder was implemented based on the legacy DSP processor. Although real-time performance was not achieved, it exposed essential computational as well memory access...

In order to solve complex algorithm that is difficult to achieve real-time processing of Multiband image fusion within large amount of data, a real-time image fusion system based on FPGA and multi-DSP is designed. Five-band image acquisition, image registration, image fusion and display output can be done within the system which uses FPGA as the main processor and the other three DSP as an algo...

This paper describes the mapping of a two-dimensional inverse discrete cosine transform (2-D IDCT) onto a wordlevel reconfigurable Montium R © processor. This shows that the IDCT is mapped onto the Montium tile processor (TP) with reasonable effort and presents performance numbers in terms of energy consumption, speed and silicon costs. The Montium results are compared with the IDCT implementat...

Efficient decoding of Dual Tone Multi-Frequency (DTMF) signals can be achieved using the sub-band non-uniform discrete Fourier transform (SB-NDFT). In this paper, the details of its implementation on the ADSP-2192 processor are put forward. The decoder performance in terms of its computational complexity and computational speed of this algorithm, implemented on the ADSP-2192 processor, are comp...

It is often seen that the available knowledge base within an organisation influences the selection of the design platform. The two major contenders for signal processing hardware platforms are DSP processor and FPGA. DSP processor offers high compute intensive complete embedded product where as FPGA offers high flexibility to a System on Programmable Chip (SoPC) designer for proof of concept at...

This paper presents a dual-core embedded System-on-Chip for a wide range of application fields with particularly high processing demands, including general signal processing, video and audio processing, and a combination of these tasks. It integrates two processor cores and various interfaces onto a single chip, all tied to a 32-bit AMBA AHB bus. The RISC core coordinates the system and perform...