A Neural Network, in general, is not considered to be a good solver of mathematical and binary arithmetic problems. However, networks have been developed for such problems as the XOR circuit. This paper presents a technique for the implementation of the Half-adder circuit using the CoActive Neuro-Fuzzy Inference System (CANFIS) Model and attempts to solve the problem using the NeuroSolutions 5 ...

This paper gives an overview of technology parameters influencing static and dynamic power consumption in modern arithmetic circuits. Also, some techniques for power minimization are presented. As an example, this paper presents the results of power consumption of binary dividers implemented in FPGAs with various technological properties.

We present reversible classical circuits for performing various arithmetic operations aided by dirty ancillae (i.e. extra qubits in an unknown state that must be restored before the circuit ends). We improve the number of clean qubits needed to factor an n-bit number with Shor’s algorithm [12] from 2n + 2 [15, 8] to n + 2, and the total number of qubits needed from 2n+2 to 2n+ 1, without increa...

In this paper we study arithmetic computations over non-associative, and non-commutative free polynomials ring F{x1, x2, . . . , xn}. Prior to this work, the non-associative arithmetic model of computation was considered by Hrubes, Wigderson, and Yehudayoff [HWY10]. They were interested in completeness and explicit lower bound results. We focus on two main problems in algebraic complexity theor...

In this paper we study arithmetic computations in the nonassociative, and noncommutative free polynomial ring F{x1, x2, . . . , xn}. Prior to this work, nonassociative arithmetic computation was considered by Hrubes, Wigderson, and Yehudayoff [HWY10], and they showed lower bounds and proved completeness results. We consider Polynomial Identity Testing (PIT) and polynomial factorization over F{x...

In design of complex arithmetic logic circuits, ground bounce noise, standby leakage current and leakage power are important and challenging issues in nanometer down scaling. In this paper, a low power, low complex and reduced ground bounce noise full adder design based on pass transistor logic (PTL) is proposed. Basically adder is vital part of complex arithmetic logic circuit in arithmetic op...

An efficient architecture of 1D CSDA MST core is designed using CSDA (Common Sharing Distributed Arithmetic) to achieve high-throughput rate supporting multistandard transformations at low cost. Common sharing distributed arithmetic (CSDA) combines factor sharing and distributed arithmetic sharing techniques, efficiently reducing the number of adders for high hardware-sharing capability. Conven...

Performance in many very-large-scale-integrated (VLSI) systems such as digital signal processing (DSP) chips, is predominantly determined by the speed of arithmetic modules like adders and multipliers. Even though redundant arithmetic algorithms produce signi"cant improvements in performance through the elimination of carry propagation, e$cient circuit implementations of these algorithms have b...

An efficient architecture of 1D CSDA MST core is designed using CSDA (Common Sharing Distributed Arithmetic) to achieve highthroughput rate supporting multistandard transformations at low cost. Common sharing distributed arithmetic (CSDA) combines factor sharing and distributed arithmetic sharing techniques, efficiently reducing the number of adders for high hardware-sharing capability. Convent...

The past decade has seen a significant interest in learning tractable probabilistic representations. Arithmetic circuits (ACs) were among the first proposed tractable representations, with some subsequent representations being instances of ACs with weaker or stronger properties. In this paper, we provide a formal basis under which variants on ACs can be compared, and where the precise roles and...