In design of complex arithmetic logic circuits, ground bounce noise, standby leakage current and leakage power are important and challenging issues in nanometer down scaling. In this paper, a low power, low complex and reduced ground bounce noise full adder design based on pass transistor logic (PTL) is proposed. Basically adder is vital part of complex arithmetic logic circuit in arithmetic op...

Parallel-prefix adders (also known as carrytree adders) are known to have the best performance in VLSI designs compared to that of conventional Ripple Carry Adder (RCA). However, each type of parallel prefix adder has its own pros and cons and are chosen according to the design requirement of the application. This paper investigates mainly two types of carry-tree adders, the brent kungg adder a...

Reversible Logic is becoming more and more prominent technology having its applications inLow Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel proposed. In all the three design approaches, the full Adder and Subtractors are realized in a sing...

The 1-bit full adder is a very important component in the design of application specific integrated circuits. Demands for the low power VLSI have been pushing the development of design methodologies aggressively to reduce the power consumption drastically. In most of the digital systems adder lies in the critical path that affects the overall speed of the system. So enhancing the performance of...

This paper presents on-chip implementation of high speed low latency floating point adder /subtractor with high accuracy performance for FFT in OFDM transceiver. However due to high performance and high resolution, the floating point adder is matched with power network applications as well. The design was implemented for 32-bit pipelined adder/subtractor which satisfied IEEE-754 Standard for fl...

http: // www.ijesrt.com© International Journal of Engineering Sciences & Research Technology [200] IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY PERFORMANCE ANALYSIS OF A LOW-POWER HIGH-SPEED HYBRID 1-BIT FULL ADDER CIRCUIT AND ITS IMPLEMENTATION Swati Narang Electronics & Communication Engineering, Indira Gandhi Delhi Technical University For Women,India DOI: 10.52...

Quantum and reversible logic circuits have more advantages than the common circuits, like low power consumption. These circuits are good choice to design future computers. One of the important issues in reversible logic is parity preservation. If parity of inputs and outputs are equal in reversible gate, this gate will be parity preserve. Reversible circuits made by these gates are parity prese...

We can overcome the CMOS scaling problems with emerging Nanotechnology. In Nanotechnology the basic building block of digital design is QCA. The problem in design of decimal adders on Quantum dot cellular automata with reduction of QCA primitives is very limited. In this paper we present a BCD adder with less number of QCA primitives and it is compared with existing BCD adder designs. Our propo...

Reversible Logic is becoming more and more prominent technology having its applications inLow Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel proposed. In all the three design approaches, the full Adder and Subtractors are realized in a sing...

This paper proposes two reversible logic gates, HNFG and HNG. The first gate HNFG can be used as two Feynman Gates. It is suitable for a single copy of two bits with no garbage outputs. It can be used as “Copying Circuit” to increase fan-out because fan-out is not allowed in reversible circuits. The second gate HNG can implement all Boolean functions. It also can be used to design optimized add...