In this paper, the Extended Coupled Amplitude Delay Lock Loop (ECADLL) architecture, previously introduced as a solution able to deal with a multipath environment, is revisited and improved to tailor it to spoofing detection purposes. Exploiting a properly-defined decision algorithm, the architecture is able to effectively detect a spoofer attack, as well as distinguish it from other kinds of i...

Migration towards a full-digital implementation of modems is currently one of the main trends in transmission systems design. In this paper we describe a non coherent a11digital delay lock loop (DDLL) suited for chip timing synchronization in band-limited direct sequence spread spectrum (DS/SS) systems, and we thoroughly analyze its performance. The key features of this novel scheme are represe...

This paper designed a tapped delay line Time-to-Digital Converter(TDC) based on 0.18μm CMOS, there is total level 128 voltage-controlled delay line.The symmetric delay phase-locked loop is used to increase the stability of delay chain and reduce the system clock’s skew and jitter. The simulation results show that : when the voltage is 1.8V, and the reference clock frequency is 250MHz, the least...

The grid frequency estimation using a recursive signal or an integrator-based method may suffer from stability issue due to accumulation discretization error. To avoid these shortcomings and also obtain robust of three-phase under unbalanced distorted conditions, this letter proposes demodulation-based without integrator. proposed approach relies on the Clarke transform fixed transport delay-ba...

In this paper, the modern nonlinear theory is applied to a third order phase locked loop (PLL) with feedback time delay. Due delay, different behaviors that are not accounted for in conventional PLL model identified, namely, oscillatory instability, periodic doubling and chaos. Firstly, Pade approximation used delay where it utilized deriving state space representation of under investigation. T...

In this paper, we propose a new algorithm for the detection of howling signal employing LMS adaptive notch filter and digital phase locked loop. The main advantages of the proposed algorithm are that it has very low computational complexity and has a short detection delay. Computer simulations are given to demonstrate the performance of this method.

A periodic clock signal is required in many ICs. These clocks are for instance used to define the sampling moments in data converters; to up-convert and down-convert the wanted signals in wireless transceivers and to synchronize the data flow in wireline and optical serial data communication links. The clock timing/phase accuracy affects the overall system performance and therefore a clock gene...

We have developed a wideband phase-locked loop (PLL) circuit with real-time phase correction for high-speed and accurate force measurements by frequency modulation atomic force microscopy (FM-AFM) in liquid. A high-speed operation of FM-AFM requires the use of a high frequency cantilever which, however, increases frequency-dependent phase delay caused by the signal delay within the cantilever e...

time-delay identification is one of the most important parameters in designing controllers. in the cases where the number of inputs and outputs in a system are more than one, this identification is of great concern. in this paper, a novel autocorrelation-based scheme for the state variable time-delay identification for multi-input multi-output (mimo) system has been presented. this method is ba...