In the previous work the problem of nding gate delays to eliminate glitches has been solved by lin ear programs LP requiring an exponentially large number of constraints By introducing two additional variables per gate namely the fastest and the slow est arrival times besides the gate delay we reduce the number of the LP constraints to be linear in circuit size For example the gate c circuit re...

Gate sizing has a significant impact on the delay, power dissipation, and area of the final circuit. It consists of choosing for each node of a mapped circuit a gate implementation in the library so that a cost function is optimized under some constraints. For instance, one wants to minimize the power consumption and/or the area of a circuit under some user-defined delay constraints, or to obta...

Abstruct-3-D technology promises higher integration density and lower interconnection complexity and delay. At present, however, not much work on circuit applications has been done due to lack of insight into 3-D circuit architecture and performance. One of the purposes of realizing 3-D integration is to reduce the interconnect complexity and delay of 2-D, which is widely avowed as the harrier ...

Reduction and for Path Delay Fault Testability Angela Krsti c and Kwang-Ting (Tim) Cheng Department of ECE, University of California, Santa Barbara, CA 93106 Abstract Path delay fault model is the most suitable model for detecting distributed manufacturing defects that can cause delay faults. However, the number of paths in a modern design can be extremely large and the path delay testability o...

This short paper describes a well-known and a non-standard technique for proving properties about sequential circuits. The techniques are based on transforming the circuit to an abstract state machine, and performing several ways of induction on these state machines. We conclude with an insightful correspondence between the two techniques. The proposed methods have been implemented in an experi...

We present a novel asynchronous RSFQ digital circuit, Test-Timed RSFQ digital circuit and system(TT), in this paper. With this asynchronous approach, data is transferred in a delay-insensitive fashion to avoid the overhead of global clock distribution and the timing uncertainty. According to the scheme, the timing signal of the logic module is generated by a test logic module. The delay module ...

In this paper, we propose a test generation method for non-robust path delay faults using stuck-at fault test generation algorithms. In our method, we first transform an original combinational circuit into a circuit called a partial leaf-dag using path-leaf transformation. Then we generate test patterns using a stuck-at fault test generation algorithm for stuck-at faults in the partial leaf-dag...

This paper proposes design of a low power sense amplifier. It is designed for the low power and delay of the circuit by using the variable threshold mos devices. Sense amplifiers are used in the memories to increase the speed for accessing data from different locations. So the speed of data read of SRAM is highly reliable on the design of sense amplifiers. The introduced circuit is tested under...

ASK Our E2E Experts WEBENCH® Calculator Tools Circuit Description This design describes the importance of accurate phase measurement between electrical signals in power automation application. The circuit utilizes a 16-bit, multiplexed input (non-simultaneous sampling) successive approximation register (SAR) based analog-to-digital converter (ADC) with an integrated analog front-end circuit for...