This paper deals with the design opportunities of Static Random Access Memory (SRAM) for lower power consumption and propagation delay. Initially the existing SRAM architectures are investigated, and thereafter a suitable basic 6T SRAM structure is chosen. The key to low power dissipation in the SRAM data path is to reduce the signal swings on the highly capacitive nodes like the bit and data l...

We present a novel input pattern generator for dynamic power network simulation. The obtained patterns successfully identify critical voltage drop areas for a set of industrial designs, which are difficult to be found using functional vectors. The search engine of the pattern generator for worst-case IR voltage drop is based on the multiobjective genetic algorithm. To achieve high coverage for ...

AhstractRapid decrease in feature sizes has increasingly accentuated the importance of matching between transistors. Deep submicron designs will further emphasize the need to focus on the effects of mismatch. Furthermore, increased efforts on high level analog device modeling will necessitate accompanying mismatch simulation and measurement methods. The deep sub-micron era forces circuit design...

This paper investigates the impact of Joule heating on the scaling trends of advanced VLSI interconnects. It shows that the interconnect Joule heating can strongly affect the maximum operating temperature of the global wires which, in turn, will constrain the scaling of current density to mitigate electromigration and, thus, greatly degrade the expected speed improvement from the use of low-k d...

As semiconductor technology strides towards billions of transistors on a single die, problems concerned with deep sub-micron process features and design productivity call for new approaches in the area of behavioural models. This paper focuses on some of recent developments and new opportunities for Petri nets in designing asynchronous circuits such as synthesis of asynchronous control circuits...

Modern high-performance cache implementations use subarrays to reduce the capacitive load on the bitlines and achieve faster access time [6]. To overlap bitline precharging time with address decoding and wordline assertion, caches typically precharge all subarrays simultaneously prior to a cache access. Though only a small number of subarrays are accessed on a cache access, precharging all suba...

This paper presents a comprehensive review of the major state-of-the-art high-speed CMOS digital circuits. Focusing in particular on dynamic circuits such as conventional DOMINO, conditionalevaluation DOMINO and contention-free DOMINO. Also some high-performance non-dynamic (static) circuit techniques will be reviewed such as dual-threshold (DVT) circuits. The relative performance of these circ...

Timing-related defects are a major cause for test escapes and field returns for very-deep-sub-micron (VDSM) integrated circuits (ICs). Small-delay variations induced by crosstalk, process variations, power-supply noise, and resistive opens and shorts can cause timing failures in a design, thereby leading to quality and reliability concerns. We present the industrial application and case study o...

IDDQ test loses its effectiveness for deep sub-micron chips since it cannot distinguish between faulty and fault-free currents. The concept of current ratios, in which the ratio of maximum to minimum IDDQ is used to screen faulty chips, has been previously proposed. However, it is incapable of screening some defects. The neighboring chips on a wafer have similar fault-free properties and are co...

High leakage current in deep sub-micron regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, leakage control and reduction are very important, especially for low power applications. The reduction in leakage current has to be achieved using both process and circuit level techn...