Many modern programmable embedded devices contain CPUs and a GPU that share the same system memory on single die. Such unified architecture (UMA) allows programmers to implement different communication models between CPU integrated (iGPU). Although simpler model guarantees implicit synchronization at cost of performance, more advanced allows, through zero-copy paradigm, explicit data copying iG...

GPU computing has emerged in recent years as a viable execution platform for throughput oriented applications or regions of code. GPUs started out as independent units for program execution but there are clear trends towards tight-knit CPU-GPU integration. In this work, we will examine existing research directions and future opportunities for chip integrated CPU-GPU systems. We first seek to un...

Interconnect Component MEM T2 HDS API Transaction Accurate Architecture T2 T3 Comm OS HAL API HDS API SystemC TLM Interconnect Component (Bus/NoC) CPU-SS1 Abstract CPU1 Periph Interface Memory Abstract CPU2 Periph Interface Memory CPU-SS2 MEM-SS T2 HDS API Comm OS HAL API T3 HAL Virtual Prototype SystemC TLM CPU-SS1 CPU1 ISS Periph Interface Memory CPU2 ISS Periph Interface Memory CPU-SS2 Inter...

We propose a design of a 16-bit RISC CPU core using an adiabatic logic which is called a two phase drive adiabatic dynamic CMOS logic (2PADCL), in this paper. The proposed adiabatic RISC CPU is non-pipelined with a latency of three cycles, and also consists of six blocks; an arithmetic and logic unit (ALU), a program counter, a register file, an instruction decoder unit, a multiplexer and a clo...

Graphic Processing Units (GPU) has been proved to be a promising platform to accelerate large size Fast Fourier Transform (FFT) computation. However, current GPU-based FFT implementation only uses GPU to compute, but employs CPU as a mere memory-transfer controller. The computation power in today’s high-performance CPU is wasted. In this project, a hybrid optimization framework is proposed to u...

The Spreadsheet CPU simulates a central processing unit for teaching purposes. The simulator provides interactive instruction execution like the “Little Man Computer,” the LC-3, and other simulators, but it is not a stand-alone program. Instead, it is implemented atop an off-the-shelf copy of the Microsoft Excel spreadsheet. The spreadsheet cells make it easy for students to observe the simulat...

With the development of synthetic aperture radar (SAR) technologies in recent years, the huge amount of remote sensing data brings challenges for real-time imaging processing. Therefore, high performance computing (HPC) methods have been presented to accelerate SAR imaging, especially the GPU based methods. In the classical GPU based imaging algorithm, GPU is employed to accelerate image proces...

Dynamic voltage scaling (DVS) allows a program to execute at a non-peak CPU frequency in order to reduce CPU power, and hence, energy consumption; however, it is oftentimes done at the expense of performance degradation. For a program whose execution time is bounded by peripherals’ performance rather than the CPU speed, applying DVS to the program will result in negligible performance penalty. ...

CPU scheduling is the basis of multi-programmed operating systems. The scheduler is accountable for multiplexing processes on the CPU. By switching the CPU among processes, the operating system results in the computer more prolific. Various CPU scheduling algorithms exist for a multi-programmed operating system like First Come First Served (FCFS), Shortest Job First (SJF), Shortest Remaining Ti...

Checkpointing and Communication Library (CCL) is a recently developed software in support of optimistic parallel discrete event simulation on myrinet clusters. Beyond low latency message delivery functionalities, CCL also offers non-blocking checkpointing functionalities supported by a programmable PCI DMA engine on board of myrinet cards. CCL employs a re-synchronization functionality between ...