Low power consumption and stability in Static Random Access Memories (SRAMs) is essential for embedded multimedia and communication applications. This paper presents a novel design flow for power minimization of nano-CMOS SRAMs, while maintaining their stability. A 32 nm High-κ/Metal-Gate SRAM has been used as example circuit. The baseline SRAM circuit is subjected to power minimization using a...

The design of a CMOS operational mirrored amplifier (OMA) suitable for high frequency applications is proposed. The CMOS operational mirrored amplifier is developed using class AB operational amplifier and two current mirrors. To obtain a wide bandwidth and high stability, HF feedforward techniques have been used. These techniques made the proposed circuit suitable for continuous – time analog ...

An analog CMOS peak detect and hold (PDH) circuit which combines high speed and accuracy, rail-to-rail sensing and driving, low power, and buffering is presented. It is based on a configuration that cancels the major error sources of the classical CMOS PDH, including offset and common mode gain, by re-using the same amplifier for tracking, peak sensing, and output buffering. By virtue of its hi...

In this paper, we implement a model of an electric fish, Eigenmannia, that detects frequency differences between the individuals, on analog CMOS circuits. The circuit’s fundamental function is equivalent to a conventional CMOS frequency comparator, although less post-processing is still required. The circuit consists of Pand T-units each of which encodes amplitudes and phases of the monitored e...

The performance of integrated circuits has been improving exponentially for more than thirty years. During the next decade, the industry must overcome several technological challenges to sustain this remarkable pace of improvement. Challenges in lithography, transistor scaling, interconnections, circuit families, computer memory, and circuit design are outlined. Possible solutions are briefly d...

There is always a need for low-power, area-efficient VLSI (Very Large-Scale Integration) design and this increasing day by day. However, conventional methods based on Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) devices Complementary (CMOS) technology cannot meet the performance requirements. The memristor, as promising computing memory integration device, offers new research idea...

This paper proposes a low voltage CMOS Nano power current reference circuit and presents its performance with circuit simulation in 180nm UMC CMOS technology. The proposed circuit consists of start-up, Bias-voltage, currentsource sub-circuits with most of the MOSFETs operating in sub-threshold region. Simulation results shows that the circuit generates a stable reference current of 4-nA in supp...

This paper presents a CMOS current-mode S-shape correction circuit. The S-shape correction function is proposed to suit for panel-to-panel LCD displays by selecting a fractional value. Simulated results are at 1.8V supply voltage for 0.35μm CMOS process. Image quality improvement due to S-shape correction is observed. The -3dB bandwidth are about 50 MHz for the proposed circuit. Key-Words: LCD,...

A new CMOS current-mode controllable low-voltage and low-power logarithmic function circuit is proposed. The circuit provides good dynamic range, controllable output, and reasonable accuracy and it is insensitive to temperature variations. The circuit operates with ±0.5 V supply, consumes 0.3 μW, and has a –3 dB frequency of 2.4 MHz. The functionality of the proposed design is confirmed using T...

AbstructA novel BiCMOS full-swing circuit technique with superior performance over CMOS down to 1.5 V is proposed. A conventional noncomplementary BiCMOS process is used. The proposed pull-up configuration is based on a capacitively coupled feedback circuit. Several pull-down options were examined and compared, and the results are reported. Several cells were implemented using the novel circuit...