The austenitic stainless steel was coated by dipping into a molten Al-12.4%Si alloy at 765oC. The effect of immersion times in the range of 60 to 900 s was investigated with respect to the phase nature, thickness, and microhardness. An uniform layer (~12 m) of Al12(Fe,Cr)3Si2 intermetallic with hexagonal crystalline structure is formed, irrespectively the immersion time. Microhardness of the c...

In this letter, a new rail-to-rail two-stage regenerative comparator for low supply voltage applications is presented. A operation achieved by utilizing an inverse inverter pre-amplifier. The proposed post-layout simulated within standard 180-nm CMOS technology. the worst-case scenario, energy efficiency and delay of are improved more than 80% compared to conventional single-stage comparator.

Improving microstructural, mechanical, and thermal properties of Ni-Co-Bronze composites is crucial for various applications. In this study, five (CuSn) + XTiC (0, 3, 7, 10, 15 wt.%) were produced by using the hot pressing method. The effect TiC reinforcement rate on each their microstructure, wear, hardness, was investigated. Within scope microstructure analysis, scanning electron microscope (...

In this paper, we report an integrated silicon-based active imaging chipset with a detector array in 0.13 m SiGe process and a CMOS-based source array operating in the 240–290 GHz range. The chipset operates at room-temperature with no external RF or optical sources, high-resistivity silicon lenses (HRSi) or waveguides or any custom fabrication options, such as high-resistivity substrates or su...

This work presents a self-timed resonant high-voltage (HV) dc–dc converter in HV CMOS silicon-on-insulator (SOI) with one-step conversion from 100–325 V input down to 3.3–10 output, optimized for applications below 500 mW, such as IoT, smart home, and e-mobility. Unlike bulky power modules, the is fully integrated, including an on-chip stage, only one external inductor (10 <inline-formula xmlns...

Designing ideal analogue circuits has become difficult due to extremely large-scale integration. The complementary metal oxide semiconductor (CMOS) analog integrated (IC) could use an evolutionary method figure out the size of each device. CMOS operational transconductance amplifier (CMOS OTA) and current conveyor second generation CCII) are designed using advanced nanometer transistor technolo...

We study a new transistor-level side-channel leakage caused by charges trapped in between stacked transistors namely residual electric (RECs). Building models is important designing countermeasures against attacks (SCAs). The conventional work showed that even measurable with local electromagnetic measurement. One example the current-path leak [1], [2]: an attacker can distinguish number of cur...

The Polder Computing Environment, a system for interactive distributed simulation K. A. Iskra1, , R. G. Belleman, G. D. van Albada, J. Santoso, P. M. A. Sloot, H. E. Bal, H. J. W. Spoelder and M. Bubak4,5 1 Section Computational Science, Universiteit van Amsterdam, Kruislaan 403, 1098 SJ Amsterdam, The Netherlands 2 Division of Mathematics and Computer Science, Faculty of Sciences, Vrije Univer...

We describe the design and CMOS implementation of a baseband spread-spectrum communication system using chaotic signals for spreading digital data. The communication system uses a new chaotic modulation scheme called M-DCSK (Modified Differential Chaos Shift Keying). The M-DCSK scheme and its characteristics are analyzed for single user and multi user applications. Results from a VLSI implement...