This paper presents a module generator for Digital/Analog Converter (DAC) circuits. A combination of circuit simulation and DAC design equations is used to estimate performance. A new constrained optimization method is used to determine design variable values. The layout is created using stretching and tiling operations on a set of primitive cells. Close coupling of optimization and layout allo...

Wire length minimization ( W L M ) has received szgnificant attention in the compaction stage of VLSI layout synthesis. In most cases, reduction in wire length also results in better circuit yield. However, a trade-off may stall exist between total wire length and yield. In WLM only the area/length of the layout patterns is considered whereas for yield enhancement both the area of the layout pa...

This paper presents an overview of recent advances on modeling and layout optimization of devices and interconnects for high-performance VLSI circuit design under the deep submicron technology. First, we review a number of interconnect and driver/gate delay models, which are most useful to guide the layout optimization. Then, we summarize the available performance optimization techniques for VL...

A computer-aided tool for the design of switching power supplies integrating layout editor, autorouter, component library builder, and EMI simulator is presented. The software takes on a modular approach and develops the printed circuit board (PCB) layout with emphasis on electromagnetic compatibility (EMC). The prediction of interference level is achieved by SPICE simulation with suitable mode...

This paper presents a mixed equation-based and simulation-based design methodology for continuous-time Sigma-Delta modulators from high level specifications down to Layout. The calculation and scaling of the SigmaDelta coefficients as well as circuit sizing and layout generation are implemented in the same analog design environment CAIRO+. The design of a complete third order current-mode conti...

We describe a hybrid method which combines the boundary element method (BEM) and the finite element method (FEM) to compute circuit models for layout dependent capacitances. The method can handle irregularities in the stratification of the layout of the integrated circuits (IC’s). New in the method are the models for the interface between the regions where the BEM and the FEM are applied. We sh...

Integrated circuits consist of active devices and an interconnection network fabricated on a semi-conducting substrate. The properties of the interconnections and the substrate are increasingly important factors affecting the performance and operation of the circuit as a whole, amplifying the need for layout verification. In this paper, we discuss the behavior of IC interconnections and substra...

This Paper presents on 3D stacking technology with 2.5μm x 2.5μm In (Indium) bump connections with adhesive injection [1]. Instead of using the simple test device, this technology has been verified using the actual circuit level test chip. And it was found that the completion of stacking process is affected by the layout pattern of stacked each tier. In order to minimize those effects, we have ...

The paper investigates the layout optimisation problem for processor-array networks. If an appropriate shape geometry is selected for the processors, a specific interconnection network can be area-eficiently mapped on a VLSI/WSI chip to maximise the chip yield, operational reliability and circuit performance. A formal technique of cellular layout by polyomino tiles is proposed, with application...