The issue of SOC testing is one of the most crucial in their design and production process. A popular solution for SOCs including microprocessor cores is based on letting them execute a test program, thus implementing a very attracting BIST solution. This paper describes a method for the generation of effective programs for the self-test of a processor starting from its RT-level description. Th...

Formulation of closed form expressions for computingMISR aliasing probability exactly had remained an unsolved problem.This paper presents single and multiple MISR aliasing probability expres-sions for arbitrary test lengths. A framework, based on algebraic codes,is developed for the analysis and synthesis of MISR-based test responsecompressors for BIST. This framework is us...

A new test pattern generator to reduce the number of transition at scan input during scan shifting is proposed. The method is based on generating more correlative neighboring bits by interchanging adjacent bits in a test pattern. The proposed work is known as Bit Interchanging Teat Pattern Generator (BI-TPG) and it consists of basic XOR, XNOR, AND gates, 2:1 Multiplexer and a register. The leng...

We present design of a two-dimensional (2-D) discrete cosine transform (DCT) circuit with built-in self-test (BIST) capability. After modifying an existing fast 2-D DCT algorithm to make it more flexible, we synthesized the data path and the controller using our high-level BIST synthesis tool and incorporated scan design to other modules. Our design achieves high fault coverage at small cost of...

© 2013 ETRI Journal, Volume 35, Number 5, October 2013 Programmable memory built-in self-test (PMBIST) is an attractive approach for testing embedded memory. However, the main difficulties of the previous works are the large area overhead and low flexibility. To overcome these problems, a new flexible PMBIST (FPMBIST) architecture that can test both single-port memory and dual-port memory using...

This paper presents a novel approach for test generation and test scheduling for multi-clock domain SoCs. A concurrent hybrid BIST architecture is proposed for testing cores. Furthermore, a heuristic for selecting cores to be tested concurrently and order of applying test patterns is proposed. Experimental results show that the proposed heuristics give us an optimized method for multi clock dom...

This paper proposes a micro-code based Programmable Memory BIST (PMBIST) architecture that can support various kinds of test algorithms. The proposed Non-linear PMBIST (NPMBIST) guarantees high flexibility and high fault coverage using not onlyMarch algorithms but also non-linear algorithms such as Walking and Galloping. This NPMBIST has an optimized hardware overhead, since algorithms can be i...

In this paper a new scheme for deterministic and mixed mode scan-based BIST is presented. It relies on a new type of test pattern generator which resembles a programmable Johnson counter and is called folding counter. Both the theoretical background and practical algorithms are presented to characterize a set of deterministic test cubes by a reasonably small number of seeds for a folding counte...

Testing of VLSI chips is changing into significantly complicated day by day as a result of increasing exponential advancement of NANO technology. BIST may be a style technique that enables a system to check mechanically itself with slightly larger system size. During this paper, the simulation result performance achieved by BIST enabled UART design through VHDL programming is enough to compensa...

Register Transfer Level Vladimir Vorisek Institute of Informatics, Slovak Academy of Sciences [email protected] Abstract The poster presents Ph.D. thesis in the area of Test Pattern Generators (TPGs) for application in distributed and embedded Built-In Self-Test (BIST). The goal of this work is to develop a general scheme of designing built-in TPGs for basic arithmetic elements such as adders...