Analysis of worst-case message transmission times in CAN networks is usually performed assuming the availability of an infinite length priority queue of message buffers at the network adapter with zero access time. In reality, adapters provide a finite number of buffers for message transmission. This paper shows how to account for the availability of a limited number of buffers at the adapter a...

A Built-In Self-Test (BIST) approach for the programmable Input/Output (I/O) buffers in Field Programmable Gate Arrays (FPGAs) is presented. The I/O buffers are tested for their various modes of operation along with their associated routing sources. A general BIST architecture, applicable to any FPGA, is presented along with the features and limitations of the approach. Experimental results are...

The delay in, or loss of, flaxseed lipoxidase activity in N-tris (hydroxymethyl) methylglycine and N-2-hydroxyethylpiperazine-N'-2-ethanesulfonic acid buffers with linolenic acid as a substrate appears due to an alteration of the lipid micelle. Flaxseed lipoxidase activity is dependent on the ionic strength of the assay solution. These effects are not observed with linoleic acid as substrate. T...

The nitrosation of acetylacetone (AcAc) has been revised in an aqueous acid medium of perchloric acid and buffers of mono-, di-, or tri-chloroacetic acid. The results show that in the presence of buffers, under conditions of [nit] ≪ [AcAc] (nit = sodium nitrite) the reaction cannot be studied by UV-Vis spectroscopy, contrary to the recently published paper by García-Rio et al. (J. Org. Chem., 2...

Methods for sizing project and feeding buffers for critical chain project management are investigated. Experiments indicate that – in the absence of bias, and for certain classes of bias – buffer consumption is independent of the mean duration of a chain. Generally the popular method – a buffer size equal to 50% of the longest path leading to it – gives rise to excessively large buffers. Buffer...

This paper investigates important problems involved in the design of a CML buffer as well as a chain of tapered CML buffers. A new design procedure to systematically design a chain of tapered CML buffers is proposed. The differential architecture of a CML buffer makes it functionally robust in the presence of environmental noise sources (e.g., crosstalk, power/ground noise). The circuit design ...

This paper presents a synthesis algorithm for pipelined circuits. The circuit is specified as a collection of independent, looselycoupled modules connected by queues. The synthesis algorithm transforms this asynchronous, modular specification into a synchronous, tightlycoupled, and fully pipelined circuit in which queues are implemented as finite buffers. Data is read from the buffers at the be...

Abshrrct: Resistance of VLSI interconnections has become significant due to large die sizes and sub-mkm geometries in high performance designs. Previous studies have proposed optimal repeater schemes wing slmple buffers for delay optimization of the interconnection. This paper proposes a more general approach that handles arbitrary logic gates as well as buffers. The methodology is based on an ...