The paper proposes a novel design of two transistor (2T) XOR gate and its application to design an 8 bit x 8 bit multiplier. The design explores the essence of suitably biasing the MOS transistor and engineering the threshold voltage of the MOS transistor through appropriate biasing and device geometry. Using the 2T XOR gates, a full adder has been realised. Detailed simulations have been carri...

Field programmable gate arrays (FPGA) are increasingly being used in the high performance and scientific computing community to implement floating-point based system. The reversible single precision floating point multiplier (RSPFPM) requires the design of reversible integer multiplier (2424) based on operand decomposition approach. Reversible logic is used to reduce the power dissipation than...

This paper is devoted to the design of a 258bit multiplier for computing pairings over Barreto-Naehrig (BN) curves at 128-bit security level. The proposed design is optimized for Xilinx field programmable gate array (FPGA). Each 258-bit integer is represented as a polynomial with five, 65 bit signed integer, coefficients . Exploiting this splitting we designed a pipelined 65-bit multiplier base...

This paper proposes a novel recursive structure block-based Wallace tree multiplier with the capability to tune its accuracy based on the precision and power requirements. The multiplier performs multiplication operations recursively from small blocks to large blocks, with a fine grain capability of turning off small blocks to trade off with power. By tuning the fidelity design “knob”, we show ...

ABSTRACT This paper introduces a digit-serial GF(2m) multiplier for use in the polynomial basis. The multiplier works with the most significant digit first and is scalable to an arbitrary digit size and can be constructed for any GF(2m). It is derived from a commonly used MSB first bit-serial multiplier, known as the standard shift-register multiplier. As the latency of the multiplier decreases...

Sub Block Parameter Name Controls Possible Values Chosen Value in_w input bit width any integer 7 corr_w correlator/output bit width any integer 12 mac_arch1 correlator architecture {0,1,2,3} 1 in_w input bit width any integer 12 out_w output bit width any integer 6 sh_w shift right bit width any integer 3 in_w input bit width any integer 6 corr_w correlator/output bit width any integer 16 mut ...

Problems facing in design migration from FPGA to standard cells design approach are discussed. Standard cell implementation of a parallel multiplier with bit-sequential input and output, using FPGA design as a prototype is considered. It is shown that careful redesign is required, because of incompatibility of the cell libraries. Also the FPGA design complexities don't present any relation to d...

In this article, a C-testable design for detecting transition faults in the polynomial basis (PB) bit parallel (BP) multiplier circuits over GF(2) is discussed. For 100 percent transition fault coverage, the proposed technique requires only 10 vectors, irrespective of multiplier size, at the cost of 6 percent extra hardware. The proposed constant test vectors which are sufficient to detect both...