. Abstract We have developed a Clock Multiplying Unit and 4 to 1 Multiplexor (CMUIMUX 4:l) that operates up to 47Gb/s. The on board VCO is LC tuned and the output clock jitter is Lpspp. The eye diagram of the output is 400mV swing with rise and fall times of less than 9ps. This integrated circuit was processed in a 120GHz BICMOS 0.25um process. Power dissipation is only 1W for a chip area of Zm...

This paper presents a general analysis of the 3rd-order nonlinearity of a differential common-emitter (CE) radio frequency (RF) amplifier and a novel way to cancel the 3rd-order nonlinearity. A SiGe BiCMOS mixer is designed based on the 3rd-order cancellation scheme. The mixer achieves +6dBm IIP3, 15dB gain and 7.7dB NF with only 2.2mA current at 2.1GHz. This performance substantially exceeds t...

This paper presents an improved master–slave bipolar Si–SiGe HBT comparator design for ultra-high-speed data converter applications. The latch is maintained during the track stage facilitating quick transition back to the latch stage, increasing the sampling speed of the comparator. Implemented in a 0.5m 55-GHz BiCMOS Si–SiGe process, this comparator consumes approximately 80 mW with sampling s...