In this work we present a test method for asynchronous circuits, based on synchronous full scan techniques. By forcing the circuit to behave synchronously in test mode, it is possible to use high-quality standard test tools and equipment. It also implies standardization and interoperability with other tools and circuits. The work resulted in an operational automatic test system for asynchronous...

Asynchronous on-chip networks are power efficient and tolerant to process variation but they are slower than synchronous on-chip networks. One reason for the low speed is the way that asynchronous routers use to build wide channels. To meet the bandwidth requirement, current routers broaden their channels by synchronizing multiple sub-channels. The C-element tree in the completion detection cir...

Asynchronous circuits without global clocks are hard to test. Scan design methods provide an effective way to test these circuits. Full scan design seems to be a perfect alternative but at the cost of area overhead. So partial scan based design helps to overcome this area overhead problem and giving a better fault coverage. This paper presents a partial scan based ATPG methodology to generate t...

The lack of methods and tools for performance estimations in asynchronous circuits is one of the main reasons why this design methodology, beside its advantages, is still unpopular among designers. Using a logic simulator it is possible to efficiently estimate all worst-case path delays in one asynchronous circuit, which can be crucial for overcoming this problem. This paper describes a method ...

Side-channel attacks are efficient attacks against cryptographic devices. They use only quantities observable from outside, such as the duration and the power consumption. Attacks against synchronous devices using electric observations are facilitated by the fact that all transitions occur simultaneously with some global clock signal. Asynchronous control remove this synchronization and therefo...

We present a unified technique for timing verification and performance analysis of complex asynchronous systems designed with implicit timing assumptions. Our method models interacting controllers and datapath elements using timing constraint graphs. Performance metrics and timing constraints to be verified are formulated as time separations between appropriate events. Separations between all r...

The problems with synchronous designs at higb clock frequencies have been well documented. This makes an asynchronous approach attractive for high speed technologies like GaAs. We investigate the issues involved by describing the design of a parallel multiplier that can be part of a floating point multiplier. We first present a new architecture called the partial array of array (PAA) that is mo...

Conventional hardware description languages do not provide all the facilities required for efficient behavioural modelling of asynchronous systems. This paper presents a new HDL incorporating CSP-like channel communication and other features making it more suitable for this task. A model of a simple microprocessor is used to illustrate how the language and tools can be applied to real design pr...

When designing asynchronous systems, the problems of hazards becomes an important issue. This paper deals with the hazard-free implementation of asynchronous logic in a look-up table based FPGA. First, the definitions of hazards and techniques to deal with them in gate-level asynchronous circuits are surveyed. Then the look-up table (LUT) model and its associated timing properties are presented...

Action systems offer a component-based approach to circuit design. Component-based approaches are well established in hardware design, but are only recently more established in software design. However, software oriented methods allow a higher level of abstraction than the often quite low-level hardware design methods used today. We propose a method to organise a large circuit derivation within...