We present tools that convert a subset of CSP into Handel-C code. Handel-C was derived from the original occam concurrency language, but has a syntax similar to the standard C programming language. It compiles to produce files to program an FPGA. We thus now have a process that can directly generate hardware from a verified high-level description. The CSP to Handel-C translator makes use of the...

In this paper, we present the design optimization of oneand two-dimensional fullypipelined computing structures for area-delaypower-efficient implementation of finite impulse response (FIR) filter by systolic decomposition of distributed arithmetic (DA)based inner-product computation. The systolic decomposition scheme is found to offer a flexible choice of the address length of the lookup-table...

Nowadays, the cryptography field is on the increase in the telecommunications world, because of this there is a constant need of more secure and efficient cryptographic algorithms. Thus, a lot of research is being done in order to try to improve the current algorithm performance. At present, one of the alternatives under research is the implementation of these algorithms in FPGAs (Field-Program...

The compilation of Handel-C programs into net-list descriptions of hardware components has been extensively used in commercial tools but never formally verified. In this paper we first introduce a variation of the existing semantic model for Handel-C compilation that is amenable for mechanical proofs and detailed enough to analyse properties about the generated hardware. We then use this model ...

The motivation behind this project is to implement a data stream processing system based on the QUAY system [1]. The prototype called QUAY-FPGA will consist of configurable hardware and software written in the Handel-C language and compiled using the DK design suite [2]. It will be demonstrated that query throughput can be improved by managing memory access patterns and increasing execution par...