In this paper are described simulation and measurement processes of a power switch cell used for single event latchup protection of a digital fault tolerant application specific integrated circuit. The standard IHP 250 nm simulation models of components are used for the performed analog simulation using the Virtuoso Cadence tools.

This paper presents an analog fault simulation approach based on concurrent fault detection. By performing fault simulation with fault dropping, high computational effort is saved. The concurrent fault detection can be applied to most analyses and is compatible with other speedupprocedures. Experimental results demonstrate the effectiveness of the presented fault simulation procedure.

This paper describes a new technique to reduce the number of simulations required during analog fault simulation. The method takes into account process parameter variations and aims to reduce the number of the computational expensive Monte Carlo simulations often required during analog fault simulation. In section I a review of the state of the art is presented, section II and III introduce the...

The accuracy of the time delay estimation using the direct correlation technique has been theoretically calculated. The random errors of the time delay estimation in digital ultrasonic measurement systems have been studied. The techniques for the time-offlight (ToF) estimation have been discussed. The theoretical equations for analog and discrete case are presented. Numerical simulation has bee...

We explore the simulation and computational capabilities of dynamical systems We rst introduce and compare several notions of simulation between discrete systems We give a general framework that allows dynamical systems to be considered as computational machines We introduce a new discrete model of computation the analog automaton model We determine the computational power of this model and pro...

This paper presents a sensitivity-based test generation tool for analog multifrequency testing and diagnosis. The test generation procedure is based on sensitivity analysis and on fault simulation. This tool generates minimal test sets that maximize the coverage of soft, large and hard component faults and that enhance the coverage of interconnect shorts. An introduction to the problem of analo...

An implementation of flexible circuit simulation through userdefined enhancements of “traditional” circuit analysis algorithms is presented. In particular, enhancements of the DC Transfer Curve analysis are used for implementation of mixed-domain simulation as required in analysis of self-heating effects of GaAs devices, while enhancements of time-domain analysis are used for simulation of mixe...

Behavioral models are used for top-down design and for bottom-up verification. The efficient simulation of large–scale dynamical system needs a systematic procedure for order reduction of the original circuit. A method based on the moment matching for behavioral model generation of analog integrated circuits and by comparison some approaches to obtain an accurate approximation of the circuit fu...

High Peak-to-Average Power Ratio (PAPR) is one of the major drawback of Orthogonal Frequency Division Multiplexing (OFDM) based systems that can cause intermodulation among the subcarriers due to the nonlinearities of the fiber. The high PAPR increases the complexity of the Analog to Digital (A/D) and Digital to Analog (D/A) converters. In this paper, I present an analysis of Discrete Fourier T...

This work evaluates the ability of OBT for detecting parametric faults in continuous-time filters. To this end, we adopt two filters with quite different topologies as cases of study and a previously reported statistical fault model. In addition, we explore the behavior of the test schemes when a particular test condition is changed. The new data reported here, obtained from a fault simulation ...