The use of forward error correction (FEC) technique is known to be an e ective way to increase the reliability of the digital communication and to improve the capacity of a channel. Convolutional encoder at the transmitter associated with the Viterbi decoder at the receiver has been a predominant FEC technique because of its high e ciency and robustness. However, the Viterbi decoder consumes la...

This paper presents the architecture and design of a high-performance asynchronous Huffman decoder for compressed-code embedded processors. In such processors, embedded programs are stored in compressed form in instruction ROM, then are decompressed on demand during instruction cache refill. The Huffman decoder is used as a code decompression engine. The circuit is non-pipelined, and is impleme...

The application of the Turbo principle in MIMO receivers allows to achieve near-capacity performance with a number of different MIMO detection algorithms. However, this high performance is paid for by a substantial increase in complexity, as detector and decoder have to be run multiple times. In this paper, we show that an analysis of detector and decoder transfer curves in the EXIT chart can b...

A Split decoding algorithm is proposed which divides each row of the parity check matrix into two or multiple nearly-independent simplified partitions. The proposed method significantly reduces the wire interconnect and decoder complexity and therefore results in fast, small, and high energy efficiency circuits. Three full-parallel decoder chips for a (2048, 1723) LDPC code compliant with the 1...

in many active noise control (anc) applications, an online secondary pathmodelling method that uses a white noise as a training signal is required. this paperproposes a new feedback anc system. here we modified both the fxlms and thevss-lms algorithms to raised noise attenuation and modelling accuracy for theoverall system. the proposed algorithm stops injection of the white noise at theoptimum...

Dolby* Digital is a high-quality audio compression format widely used in feature films and, more recently, on DVD. PCs now offer DVD drives, and providing a Dolby Digital decoder in software allows decoding of Dolby Digital to become a baseline capability on the PC. Intel’s MMXTM technology provides instructions that can significantly speed up the execution of the Dolby Digital decoder, freeing...

We propose an area-efficient high-speed interleaved Viterbi decoder architecture, which is based on the state-parallel architecture with register exchange path memory structure, for interleaved convolutional code. The state-parallel architecture uses as many add-compare-select (ACS) units as the number of trellis states. By replacing each delay (or storage) element in state metrics memory (or p...

Presented in this paper is a pipelined 285-MHz maximum a posteriori probability (MAP) decoder IC. The 8.7-mm IC is implemented in a 1.8-V 0.18m CMOS technology and consumes 330 mW at maximum frequency. The MAP decoder chip features a block-interleaved pipelined architecture, which enables the pipelining of the add-compare-select kernels. Measured results indicate that a turbo decoder based on t...

An optimized memory organization has been designed for the hierarchical coding of wavelet subbands. A better economy in time and resources can be accomplished by changing the RAM access pattern and using multiple location access at each clock instant. The bit-planes are distributed along the z-direction and the x − y plane contains 256 × 256 number of memory elements. The memory plane selection...

The IS-95 Direct Sequence Code Division Multiple Access (DS-CDMA) system has become a U.S. digital cellular standard. In the forward traffic channels (from the base station to the mobiles), the speech encoder rate can vary, depending on the speech activity in the transmitter. At the receiver, the decoder does not know which one of the speech encoder rate the transmitter used. This paper focuses...