We propose a time-to-digital converter (TDC) using a charge pump and a SAR-ADC. With this architecture, high time resolution is attainable by increasing the charging current or reducing the sampling capacitance. Thus, the resolution limitation in a delay-chain TDC does not exist. We propose to use a SAR-ADC attributed to its characteristics of compact structure, scalability, low power consumpti...

We introduce a unique bandpass ΣΔ based common module with reconfigurable, bit-stream based digital beam-forming (DBF). An array of bandpass ΣΔ modulators accurately and efficiently digitizes the IF signals. Beam-forming is implemented directly through bitsteam processing of the fast, low-resolution bit-stream outputs of the quantizers of each bandpass ΣΔ modulator. Fabricated in 65nm CMOS, the...

Spectrally Efficient FDM (SEFDM) systems employ non-orthogonal overlapped carriers to improve spectral efficiency for future communication systems. One of the challenges for SEFDM systems is to demonstrate efficient hardware implementations for transmitters and receivers. This paper presents the first VLSI digital baseband transmitter architecture for SEFDM. The transmitter is reconfigurable be...

An ULP back-channel receiver is presented that demodulates binary a FSK back-channel signal embedded in 5.8GHz IEEE 802.11a Wi-Fi OFDM packets. The architecture of the back-channel receiver employs a two-step downconversion where the first mixing stage downconverts using the 3rd harmonic of the LO for power efficiency. The LP-65nm CMOS receiver consumes 335μW with a sensitivity of -72dBm at a B...

A magnetoelectric antenna (ME) can exhibit the dual capabilities of wireless energy harvesting and sensing at different frequencies. In this article, a behavioral circuit model for hybrid ME antennas is described to emulate radio frequency (RF) operations during simulations. The work interfaced with CMOS harvester chip towards goal developing communication link fully integrated implantable devi...

Advanced Architectures for Efficient mm-Wave CMOS Wireless Transmitters by Jiashu Chen Doctor of Philosophy in Engineeing Electrical Engineeing and Computer Sciences University of California, Berkeley Professor Ali M. Niknejad, Chair With fast growing consumer demand for high speed mobile data capacity, wireless spectrum has become increasingly precious. This drives the evolution of the persona...

This article describes low latency, zero overhead DFE burst error correction technique. Without any encoder or decoder the proposed technique makes use of existing pre-cursor ISI to detect and correct errors on a data. The implemented proof-of-concept 2-tap prototype in 65nm CMOS operates at 16 Gb/s compensates 32 dB loss consuming 58 mW only. With an additional 18 mW, receiver enables capabili...

With the continuous scaling down of transistor feature sizes, the semiconductor industry faces new challenges. One of these challenges is the incessant increase of power consumption in integrated circuits. This problem has motivated the industry and academia to pay significant attention to low-power circuit design for the past two decades. Operating digital circuits at lower voltage levels was ...

Embedded SRAMs are a critical component in modern digital systems, and their role is preferentially increasing. As a result, SRAMs strongly impact the overall power, performance, and area, and, in order to manage these severely constrained trade-offs, they must be specially designed for target applications. Highly energy-constrained systems (e.g. implantable biomedical devices, multimedia hands...

Towards an Ultra-Low Energy Computation with Asynchronous Circuits by Tsung-Te Liu Doctor of Philosophy in Engineering Electrical Engineering and Computer Sciences University of California, Berkeley Professor Jan M. Rabaey, Chair Emerging biomedical applications would benefit from the availability of digital processors with substantially improved energy-efficiency. One approach to realize ultra...