As the standby supply voltage for the static RAM (SRAM) design scales down for the low-power purpose, the static noise margin of SRAM also decreases. If the supply voltage is below the data retention voltage (DRV), the data need to be checked and corrected before they are sent out of the memory block. In this project, we study the effect of implemented error correction code (ECC) technique to t...

SRAM-based FPGAs are increasingly becoming more popular in applications where high dependability, low cost, and fast time-tomarket are important constraints. However, these devices are more susceptible to single-event upsets (SEUs) compared ASIC designs. The error models of SRAM-based due to SEUs are more complicated than those of ASICs since soft-errors in the configuration memory result in pe...

The paper investigates on the design aspects of different SRAM cells for access time, power consumption and static noise margin. All the designs are made by using standard 90nm CMOS process. Simulations have been done for 6T, 7T, 9T and 10T SRAM cells. 10T SRAM cell shows the best SNM among all the simulated cells. 9T shows least power and least access time. 6T cells stability limits the potent...

Ternary content-addressable memory (TCAM) is often used in high speed search intensive applications such as ATM switch, IP filters. Hence, currently ZTCAM, is introduced which emulates the TCAM functionality with SRAM. It has some drawbacks such as low scalability, low storage density, slow access time and high cost. But this paper proposes novel memory architecture of existing Z-TCAM, but with...

Our present research endeavor focuses on the factors of hybrid single electron transistor (SET)-CMOS based static random access memory (SRAM). Ultra small low power dissipated SET is combined with high gain and high current drivable CMOS and the write operation of the memory cell is briefly analyzed. This work is a comparative work of power consumption between conventional CMOS based SRAM and h...

This paper compares areas between a 6T and 8T SRAM cells, in a dual-Vdd scheme and a dynamic voltage scaling (DVS) scheme. In the dual-Vdd scheme, we predict that the area of the 6T cell keep smaller than that of the 8T cell, over feature technology nodes all down to 32 nm. In contrast, in the DVS scheme, the 8T cell will becomes superior to the 6T cell after the 32-nm node, in terms of the are...

A testing system has been designed to detect the single event upset failure of SRAM chips in this paper: a visual test bench for failure monitoring is developed based on LabVIEW, it could perform the task of data acquisition, storage and results analysis. At the testing board, the test vectors based on March Calgorithm are written to the reference SRAM and the under-test SRAM through FPGA. NI H...

This paper describes a novel memory hierarchy and line-pixel-lookahead (LPL) for an H.264/AVC video decoder. The memory system is the bottleneck of most video processors, particularly in the newly announced H.264/AVC. This is because it utilizes the neighboring pixels to create a reliable predictor, leading to a dependency on a long past history of data. This problem can be resolved by allocati...

In this paper, a multi-level wordline driver scheme is presented to improve 6T-SRAM read and write stability. The proposed wordline driver generates a shaped pulse during the read mode and a boosted wordline during the write mode. During read, the shaped pulse is tuned at nominal voltage for a short period of time, whereas for the remaining access time, the wordline voltage is reduced to save t...

A 135mV 0.13W process tolerant 6T subthreshold DTMOS SRAM in 90nm technology" Abstract Cell stability and tolerance to process variation are of primary importance in subthreshold SRAMs. We propose a DTMOS based 6T SRAM suitable for subthreshold operation. For variation tolerant memory peripheral circuitry, we apply β-ratio modulation technique. DTMOS SRAM array fabricated in 90nm technology ope...