Decreasing power consumption is the key design issue of SSDs. A typical SSD consists of more than 16 NAND Flash memories, DRAMs and a NAND controller. Since the NAND write performance is 10MB/s [1,2], to raise the write speed of SSD to the level of HDD, 100MB/s, 8 or more NAND chips in SSD are simultaneously programmed. As the feature size decreases, the total bitline capacitance in a chip incr...

The evolution of data storage technologies has been extraordinary. Hard disk drives that fit in current personal computers have the capacity that requires tons of transistors to achieve in 1970s. Today, we are at the beginning of the era of non-volatile memory (NVM). NVMs provide excellent performance such as random access, high I/O speed, low power consumption, and so on. The storage density o...

The limited lifespan is the Achilles’s heel of Solid State Drive (SSD) based on NAND flash memory. NAND flash has two drawbacks that degrade SSD’s lifespan. One is the out-of-place update. Another is the sequential write constraint within a block. To extend the lifespan, SSD usually employs a write buffer to reduce write traffic to flash memory. However, existing write buffer schemes only pay a...

By microscopically observing widely used data files, we identified the considerable room for life time improvement in NAND flash memory, which is due to the discovery of a non-uniformity in bit-level data patterns. In an attempt to exploit the discovery, we propose a novel bit-level wear-leveling scheme. Instead of considering only the view of page-level or block-level, we incorporate the nonun...

In this paper the process step and analysis of bit cost of stacked type MRAM with NOR structured cell has been newly described. For NOR structure 4 layer process is needed for realizing 1 layer memory cell compared with 2 layer for NAND structure. Estimated bit cost for stacked type NOR MRAM is very small, 0.04-0.4, compared with that of 1 layered NAND flash memory. This shows that not only NAN...