We present a novel 4-2 compressor for designing multi-operand addition circuits. The design is based on a current mode circuit from which the equivalent voltage mode circuit is derived. This circuit can be used to build very fast multi-operand addition structures. We provide a gate level cost and speed comparison between our design and existing 4-2 compressors. Also, we make an analytical compa...

This paper presents a systematic theoretical approach for the analysis of bounds on power consumption in Baugh-Wooley, binary tree and Wallace tree multi-pliers. This is achieved by rst developing state transition diagrams (STDs) for the sub-circuits making up the multipliers. The STD is comprised of states and edges, with the edges representing a transition (switching activity) from one state ...

Two algorithms for minimum cut linear arrangement of a class of graphs called p-q dags are proposed. A p-q dag represents the connection scheme of an adder tree, such as Wallace tree, and the VLSI layout problem of a bit slice of an adder tree is treated as the minimum cut linear arrangement problem of its corresponding p-q dag. One of the two algorithms is based on dynamic programming. It calc...

We eliminate a key roadblock to efficient verification of nonlinear integer arithmetic using CDCL SAT solvers, by showing how to construct short resolution proofs for many properties of the most widely used multiplier circuits. Such short proofs were conjectured not to exist. More precisely, we give n size regular resolution proofs for arbitrary degree 2 identities on array, diagonal, and Booth...

An energy-efficient power-aware design is highly desirable for DSP functions that encounter a wide diversity of operating scenarios in battery-powered wireless sensor network systems. Addressing this issue, this letter presents a low-power power-aware scalable pipelined Booth multiplier that makes use of dynamic-range detection unit, sharing common functional units, ensemble of optimized Wallac...

Multiplication is an arithmetic operation that has a meaningful impact on the performance of several real-life applications, such as digital signal and image processing. Analysis comparison different types fixed-point multipliers Wallace tree, array, Booth-2 with truncated non-truncated versions were included in this design. Fixed-point used to design floating-point through hardware description...

In this paper we present a VHDL code generator for a complex multiplier. The complex multiplier is based on a bit-parallel version of distributed arithmetic which reduces the hardware by nearly half compared to a straightforward implementation based on real multipliers. We choose an Overturned-Stairs adder tree to perform the summations in distributed arithmetic. The tree has a regular structur...