There have been great advances in integrated circuits technology in recent years which have both made feasible and generated major interest in electronic circuits which employ more than two levels of signals. These circuits, called multiple valued logic circuits, offer several potential oppourtinities for the improvement of VLSI circuit designs. In this paper we review developments and potentia...

In this paper, we present a methodology to explore and evaluate the crosstalk noise and the profile of its variations, and the delay of interconnects through investigation of two groups of interconnect structures in nano scale VLSI circuits. The interconnect structures in the first group are considered to be partially coupled identical lines. In this case, by choosing proper values for differen...

Multiple valued logic (MVL) has been proposed as a means for reducing the power, improving the speed, and increasing the packing density of VLSI circuits. These performance improvements are achieved by designers who identify signal processing functions that can benefit from the design tradeoffs possible with MVL. Since advocates of MVL are accustomed to incorporating the possible tradeoffs of M...

Buses of CMOS VLSI Circuits Harish Kriplani, Farid Najm and Ibrahim Hajj Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign Abstract: This paper summarizes the main developments of our on going study at University of Illinois on the maximum voltage drop estimation in power and ground buses of CMOS VLSI circuits. Voltage drops occurring in the supply li...

An Introduction to Logic Circuit Testing provides a detailed coverage of techniques for test generation and testable design of digital electronic circuits/systems. The material covered in the book should be sufficient for a course, or part of a course, in digital circuit testing for senior-level undergraduate and first-year graduate students in Electrical Engineering and Computer Science. The b...

In this paper, we present an algorithm for computing the bounds on energy-efficiency of digital very large scale integration (VLSI) systems in the presence of deep submicron noise. The proposed algorithm is based on a soft-decision channel model of noisy VLSI systems and employs information–theoretic arguments. Bounds on energy-efficiency are computed for multimodule systems, static gates, dyna...

Very large scale integration (VLSI) circuit comprises of integrated circuit (IC) with transistors in a single chip, widely used in many sophisticated electronic devices. In our paper, we proposed VLSI circuit design by implementing satisfiability problem in Hopfield neural network as circuit verification technique. We restrict our logic construction to 2-Satisfiability (2-SAT) and 3Satisfiabili...

As technology scales down, digital VLSI circuits are prone to many manufacturing defects. These defects may result in functional and delay-related circuit failures. The number of test escapes grows when is downscaled. Small delay (SDDs) hidden (HDDs) critical importance industries today since they the source most reliability problems. Improving quality creating new methods, algorithms, designs ...