This paper describes the field programmable gate array (FPGA) implementation of a fast 2-D discrete cosine transform (DCT) chip for higher image compression ratio. The development of encoding and decoding parts of 2-D DCT algorithm is carried out by using Matlab simulation tools and VHSIC hardware descriptive language (VHDL). Comparisons of results for higher image compression ratio as obtained...

Modern chips may contain a large number of embedded test, debugging, configuration, and monitoring features, called instruments. An instrument and its instrument access procedures may be pre-developed and reused, and each instrument—in different chips and through the life-time of a chip—may be accessed in different ways, which requires retargeting. To address reuse and retargeting of instrument...

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The coverification of a given HW/SW system consists of checking whether the implementation of the software and hardware parts and their integration fulfill or not some or all the specification requirements of this system. In the case of a distributed model, the SW and HW system blocks are described respectively by HLL (High Level Language) and HDL (Hardware Description Language) codes. When dea...

This tutorial describes how Altera's Quartus R II software deals with the timing issues in designs based on the Verilog hardware description language. It discusses the various timing parameters and explains how specific timing constraints may be set by the user.

The use of standard languages like VHDL and C for the description of hardware and software IP has became a common practice. Despite this, these languages, specially the hardware description languages lack constructs that allow the IP designer to develop highly re-usable IP blocks. In this paper is described an abstract communication mechanism that uses extensions to the VHDL language, communica...

Volume 16, No. 1 TRANSACTIONS 1